Lines Matching +full:0 +full:x20a00
31 #define HCLGE_INVALID_VPORT 0xffff
37 #define HCLGE_VECTOR_REG_BASE 0x20000
38 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000
39 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
41 #define HCLGE_VECTOR_REG_OFFSET 0x4
42 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
43 #define HCLGE_VECTOR_VF_OFFSET 0x100000
45 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
48 #define HCLGE_GRO_EN_REG 0x28000
49 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008
52 #define HCLGE_RING_RX_ADDR_L_REG 0x80000
53 #define HCLGE_RING_RX_ADDR_H_REG 0x80004
54 #define HCLGE_RING_RX_BD_NUM_REG 0x80008
55 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
56 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014
57 #define HCLGE_RING_RX_TAIL_REG 0x80018
58 #define HCLGE_RING_RX_HEAD_REG 0x8001C
59 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020
60 #define HCLGE_RING_RX_OFFSET_REG 0x80024
61 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
62 #define HCLGE_RING_RX_STASH_REG 0x80030
63 #define HCLGE_RING_RX_BD_ERR_REG 0x80034
64 #define HCLGE_RING_TX_ADDR_L_REG 0x80040
65 #define HCLGE_RING_TX_ADDR_H_REG 0x80044
66 #define HCLGE_RING_TX_BD_NUM_REG 0x80048
67 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C
68 #define HCLGE_RING_TX_TC_REG 0x80050
69 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054
70 #define HCLGE_RING_TX_TAIL_REG 0x80058
71 #define HCLGE_RING_TX_HEAD_REG 0x8005C
72 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060
73 #define HCLGE_RING_TX_OFFSET_REG 0x80064
74 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068
75 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
76 #define HCLGE_RING_TX_BD_ERR_REG 0x80074
77 #define HCLGE_RING_EN_REG 0x80090
80 #define HCLGE_TQP_INTR_CTRL_REG 0x20000
81 #define HCLGE_TQP_INTR_GL0_REG 0x20100
82 #define HCLGE_TQP_INTR_GL1_REG 0x20200
83 #define HCLGE_TQP_INTR_GL2_REG 0x20300
84 #define HCLGE_TQP_INTR_RL_REG 0x20900
103 #define HCLGE_PHY_PAGE_MDIX 0
104 #define HCLGE_PHY_PAGE_COPPER 0
135 #define PF_VPORT_ID 0
137 #define HCLGE_PF_ID_S 0
138 #define HCLGE_PF_ID_M GENMASK(2, 0)
142 #define HCLGE_NETWORK_PORT_ID_S 0
143 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
146 #define HCLGE_PF_OTHER_INT_REG 0x20600
147 #define HCLGE_MISC_RESET_STS_REG 0x20700
148 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
149 #define HCLGE_GLOBAL_RESET_REG 0x20A00
150 #define HCLGE_GLOBAL_RESET_BIT 0
154 #define HCLGE_FUN_RST_ING 0x20C00
155 #define HCLGE_FUN_RST_ING_B 0
158 #define HCLGE_VECTOR0_REG_PTP_INT_B 0
164 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
174 #define HCLGE_TQP_MEM_SIZE 0x10000
187 #define HCLGE_SUPPORT_1G_BIT BIT(0)
244 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
263 HCLGE_HILINK_H32 = 0,
267 #define QUERY_SFP_SPEED 0
288 u8 speed_type; /* 0: sfp speed, 1: active speed */
322 #define HCLGE_FILTER_TYPE_VF 0
324 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
325 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
345 #define HCLGE_LINK_STATUS_DOWN 0
349 #define HCLGE_SCH_MODE_SP 0
353 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
361 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
405 /* mac stats ,opcode id: 0x0032 */
522 /* fec stats ,opcode id: 0x0316 */
645 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)
646 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)
647 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)
848 * | 0 | 0 | always hit |
850 * | 1 | 0 | match '0' |
852 * | 0 | 1 | match '1' |
941 #define HCLGE_FLAG_MAIN BIT(0)
1057 u32 bw_limit; /* VSI BW Limit (0 = disabled) */