| /linux-6.12.1/drivers/staging/rts5208/ |
| D | ms.h | 19 #define MS_EXTRA_SIZE 0x9
21 #define WRT_PRTCT 0x01
24 #define MS_NO_ERROR 0x00
25 #define MS_CRC16_ERROR 0x80
26 #define MS_TO_ERROR 0x40
27 #define MS_NO_CARD 0x20
28 #define MS_NO_MEMORY 0x10
29 #define MS_CMD_NK 0x08
30 #define MS_FLASH_READ_ERROR 0x04
31 #define MS_FLASH_WRITE_ERROR 0x02
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen5/ |
| D | decode.json | 4 "EventCode": "0xa9",
9 "EventCode": "0xaa",
11 "UMask": "0x01"
15 "EventCode": "0xaa",
17 "UMask": "0x02"
21 "EventCode": "0xaa",
23 "UMask": "0x07"
27 "EventCode": "0xab",
29 "UMask": "0x04"
33 "EventCode": "0xab",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | other.json | 4 "EventCode": "0x96",
9 "EventCode": "0xa9",
14 "EventCode": "0xaa",
16 "UMask": "0x01"
20 "EventCode": "0xaa",
22 "UMask": "0x02"
26 "EventCode": "0xaa",
28 "UMask": "0x04"
32 "EventCode": "0xaa",
34 "UMask": "0x07"
[all …]
|
| /linux-6.12.1/drivers/media/platform/chips-media/coda/ |
| D | coda_regs.h | 14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
|
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | omap5.h | 8 #define OMAP5_CLKCTRL_OFFSET 0x20
12 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
15 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
18 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
19 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
20 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
21 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
22 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
23 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
24 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
[all …]
|
| D | omap4.h | 8 #define OMAP4_CLKCTRL_OFFSET 0x20
12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
[all …]
|
| D | dra7.h | 8 #define DRA7_CLKCTRL_OFFSET 0x20
12 #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
15 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
18 #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
21 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
23 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
24 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
25 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
26 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
27 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
[all …]
|
| /linux-6.12.1/Documentation/mm/ |
| D | page_owner.rst | 78 post_alloc_hook+0x177/0x1a0
79 get_page_from_freelist+0xd01/0xd80
80 __alloc_pages+0x39e/0x7e0
81 allocate_slab+0xbc/0x3f0
82 ___slab_alloc+0x528/0x8a0
83 kmem_cache_alloc+0x224/0x3b0
84 sk_prot_alloc+0x58/0x1a0
85 sk_alloc+0x32/0x4f0
86 inet_create+0x427/0xb50
87 __sock_create+0x2e4/0x650
[all …]
|
| /linux-6.12.1/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm.c | 27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
[all …]
|
| /linux-6.12.1/drivers/clk/meson/ |
| D | s4-pll.h | 10 #define ANACTRL_FIXPLL_CTRL0 0x040
11 #define ANACTRL_FIXPLL_CTRL1 0x044
12 #define ANACTRL_FIXPLL_CTRL3 0x04c
13 #define ANACTRL_GP0PLL_CTRL0 0x080
14 #define ANACTRL_GP0PLL_CTRL1 0x084
15 #define ANACTRL_GP0PLL_CTRL2 0x088
16 #define ANACTRL_GP0PLL_CTRL3 0x08c
17 #define ANACTRL_GP0PLL_CTRL4 0x090
18 #define ANACTRL_GP0PLL_CTRL5 0x094
19 #define ANACTRL_GP0PLL_CTRL6 0x098
[all …]
|
| D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
|
| /linux-6.12.1/drivers/tty/serial/8250/ |
| D | 8250_fourport.c | 16 SERIAL8250_FOURPORT(0x1a0, 9),
17 SERIAL8250_FOURPORT(0x1a8, 9),
18 SERIAL8250_FOURPORT(0x1b0, 9),
19 SERIAL8250_FOURPORT(0x1b8, 9),
20 SERIAL8250_FOURPORT(0x2a0, 5),
21 SERIAL8250_FOURPORT(0x2a8, 5),
22 SERIAL8250_FOURPORT(0x2b0, 5),
23 SERIAL8250_FOURPORT(0x2b8, 5),
|
| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
|
| D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
|
| D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
|
| /linux-6.12.1/Documentation/fault-injection/ |
| D | nvme-fault-injection.rst | 33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
|
| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-qserdes-txrx-v7.h | 9 #define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
11 #define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
12 #define QSERDES_V7_TX_TX_BAND 0x24
13 #define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
14 #define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
15 #define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
16 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
17 #define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
18 #define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
[all …]
|
| D | phy-qcom-qmp-qserdes-txrx-v6.h | 9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
|
| D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
|
| /linux-6.12.1/arch/xtensa/include/asm/ |
| D | mxregs.h | 20 * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p
21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
22 * 0180 0...0m..m Clear enable specified by mask (m)
23 * 0184 0...0m..m Set enable specified by mask (m)
24 * 0190 0...0x..x 8-bit IPI partition register
30 * 0200 0...0m..m RunStall core 'n'
34 #define MIROUT(irq) (0x000 + (irq))
35 #define MIPICAUSE(cpu) (0x100 + (cpu))
36 #define MIPISET(cause) (0x140 + (cause))
37 #define MIENG 0x180
[all …]
|
| /linux-6.12.1/tools/power/cpupower/utils/helpers/ |
| D | msr.c | 12 #define MSR_IA32_PERF_STATUS 0x198
13 #define MSR_IA32_MISC_ENABLES 0x1a0
14 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1ad
19 * Will return 0 on success and -1 on failure.
33 if (fd < 0) in read_msr()
40 return 0; in read_msr()
49 * Will return 0 on success and -1 on failure.
62 if (fd < 0) in write_msr()
69 return 0; in write_msr()
|
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_doorbell.h | 100 AMDGPU_DOORBELL_KIQ = 0x000,
101 AMDGPU_DOORBELL_HIQ = 0x001,
102 AMDGPU_DOORBELL_DIQ = 0x002,
103 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
104 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
105 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
106 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
107 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
108 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
109 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
|
| /linux-6.12.1/include/linux/mfd/ |
| D | idt82p33_reg.h | 10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
[all …]
|
| /linux-6.12.1/drivers/scsi/mvsas/ |
| D | mv_94xx.h | 18 VANIR_A0_REV = 0xA0,
19 VANIR_B0_REV = 0x01,
20 VANIR_C0_REV = 0x02,
21 VANIR_C1_REV = 0x03,
22 VANIR_C2_REV = 0xC2,
26 MVS_HST_CHIP_CONFIG = 0x10104, /* chip configuration */
30 MVS_GBL_CTL = 0x04, /* global control */
31 MVS_GBL_INT_STAT = 0x00, /* global irq status */
32 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
34 MVS_PHY_CTL = 0x40, /* SOC PHY Control */
[all …]
|
| /linux-6.12.1/drivers/usb/fotg210/ |
| D | fotg210-udc.h | 14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
|