Lines Matching +full:0 +full:x1a0
14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
32 #define FOTG210_DAR 0x104
35 /* Device Test Register(0x108) */
36 #define FOTG210_DTR 0x108
37 #define DTR_TST_CLRFF (1 << 0)
39 /* PHY Test Mode Selector register(0x114) */
40 #define FOTG210_PHYTMSR 0x114
45 #define PHYTMSR_UNPLUG (1 << 0)
47 /* Cx configuration and FIFO Empty Status register(0x120) */
48 #define FOTG210_DCFESR 0x120
54 #define DCFESR_CX_DONE (1 << 0)
56 /* Device IDLE Counter Register(0x124) */
57 #define FOTG210_DICR 0x124
59 /* Device Mask of Interrupt Group Register (0x130) */
60 #define FOTG210_DMIGR 0x130
63 #define DMIGR_MINT_G0 (1 << 0)
65 /* Device Mask of Interrupt Source Group 0(0x134) */
66 #define FOTG210_DMISGR0 0x134
70 #define DMISGR0_MCX_SETUP_INT (1 << 0)
72 /* Device Mask of Interrupt Source Group 1 Register(0x138)*/
73 #define FOTG210_DMISGR1 0x138
86 #define DMISGR1_MF0_OUT_INT (1 << 0)
87 #define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2)
89 /* Device Mask of Interrupt Source Group 2 Register (0x13C) */
90 #define FOTG210_DMISGR2 0x13C
94 /* Device Interrupt group Register (0x140) */
95 #define FOTG210_DIGR 0x140
98 #define DIGR_INT_G0 (1 << 0)
100 /* Device Interrupt Source Group 0 Register (0x144) */
101 #define FOTG210_DISGR0 0x144
107 #define DISGR0_CX_SETUP_INT (1 << 0)
109 /* Device Interrupt Source Group 1 Register (0x148) */
110 #define FOTG210_DISGR1 0x148
115 /* Device Interrupt Source Group 2 Register (0x14C) */
116 #define FOTG210_DISGR2 0x14C
125 #define DISGR2_USBRST_INT (1 << 0)
127 /* Device Receive Zero-Length Data Packet Register (0x150)*/
128 #define FOTG210_RX0BYTE 0x150
136 #define RX0BYTE_EP1 (1 << 0)
138 /* Device Transfer Zero-Length Data Packet Register (0x154)*/
139 #define FOTG210_TX0BYTE 0x154
147 #define TX0BYTE_EP1 (1 << 0)
149 /* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
150 #define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1))
151 #define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF)
155 /* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
156 #define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1))
158 /* Device Endpoint 1~4 Map Register (0x1A0) */
159 #define FOTG210_EPMAP 0x1A0
161 ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
163 ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
165 /* Device FIFO Map Register (0x1A8) */
166 #define FOTG210_FIFOMAP 0x1A8
167 #define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8)
168 #define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8)
169 #define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8)
170 #define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8)
172 #define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8)
174 /* Device FIFO Confuguration Register (0x1AC) */
175 #define FOTG210_FIFOCF 0x1AC
177 #define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2)
178 #define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2)
179 #define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2)
180 #define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4)
181 #define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4)
182 #define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5)
184 /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
185 #define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4)
186 #define FIBCR_BCFX 0x7FF
189 /* Device DMA Target FIFO Number Register (0x1C0) */
190 #define FOTG210_DMATFNR 0x1C0
195 #define DMATFNR_ACC_F0 (1 << 0)
197 #define DMATFNR_DISDMA 0
199 /* Device DMA Controller Parameter setting 1 Register (0x1C8) */
200 #define FOTG210_DMACPSR1 0x1C8
201 #define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8)
203 #define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1)
204 #define DMACPSR1_DMA_START (1 << 0)
206 /* Device DMA Controller Parameter setting 2 Register (0x1CC) */
207 #define FOTG210_DMACPSR2 0x1CC
209 /* Device DMA Controller Parameter setting 3 Register (0x1CC) */
210 #define FOTG210_CXPORT 0x1D0
249 u8 ep0_dir; /* 0/0x80 out/in */