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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_4_0_smn.h26 // base address: 0x10100000
27 #define smnBIFL_RAS_CENTRAL_STATUS 0x10139040
29 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
30 #define smnCPM_CONTROL 0x11180460
31 #define smnPCIE_CNTL2 0x11180070
32 #define smnPCIE_CI_CNTL 0x11180080
34 #define smnPCIE_PERF_COUNT_CNTL 0x11180200
35 #define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
36 #define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
37 #define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
[all …]
Dnbio_7_11_0_offset.h29 // base address: 0x0
30 …NBCFG_SCRATCH_0 0x0068
31 …NBCFG_SCRATCH_1 0x006c
32 …NBCFG_SCRATCH_2 0x0070
33 …NBCFG_SCRATCH_3 0x0074
34 …NBCFG_SCRATCH_4 0x0078
38 // base address: 0x0
42 // base address: 0x0
43 …PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0580
47 // base address: 0x13b00000
[all …]
Dnbio_7_9_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
/linux-6.12.1/arch/arm/boot/dts/arm/
Darm-realview-eb-11mp-ctrevb.dts38 reg = <0x10101000 0x1000>,
39 <0x10100100 0x100>;
43 reg = <0x10102000 0x1000>;
47 reg = <0x10100000 0x100>;
51 reg = <0x10100600 0x20>;
55 reg = <0x10100620 0x20>;
Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
38 #size-cells = <0>;
40 port@0 {
41 reg = <0>;
71 reg = <0x10000000 0x200>;
72 ranges = <0x0 0x10000000 0x200>;
76 led@8,0 {
78 reg = <0x08 0x04>;
79 offset = <0x08>;
[all …]
/linux-6.12.1/arch/mips/boot/dts/mscc/
Dluton.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x60000000 0x20000000>;
56 reg = <0x10000000 0x2c>;
61 reg = <0x10000084 0x70>;
69 pinctrl-0 = <&uart_pins>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/usb/
Dstarfive,jh7110-usb.yaml68 "^usb@[0-9a-f]+$":
88 ranges = <0x0 0x10100000 0x100000>;
91 starfive,stg-syscon = <&stg_syscon 0x4>;
105 usb@0 {
107 reg = <0x0 0x10000>,
108 <0x10000 0x10000>,
109 <0x20000 0x10000>;
/linux-6.12.1/arch/arm/mach-nomadik/
Dcpu-8815.c17 #define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
18 #define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
19 #define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
20 #define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
21 #define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
22 #define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
23 #define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
24 #define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
25 #define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
26 #define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-ralink/
Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/linux-6.12.1/arch/arm64/boot/dts/realtek/
Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
51 soc@0 {
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
[all …]
Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
50 soc@0 {
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
[all …]
Drtd16xx.dtsi23 reg = <0x2f000 0x1000>;
27 reg = <0x1ffe000 0x4000>;
31 reg = <0x10100000 0xf00000>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
51 reg = <0x100>;
59 reg = <0x200>;
67 reg = <0x300>;
75 reg = <0x400>;
[all …]
/linux-6.12.1/drivers/staging/rtl8712/
Drtl871x_pwrctrl.c23 #define RTL8712_SDIO_LOCAL_BASE 0X10100000
24 #define SDIO_HCPWM (RTL8712_SDIO_LOCAL_BASE + 0x0081)
32 if (pwrpriv->rpwm_retry == 0) in r8712_set_rpwm()
52 pwrpriv->rpwm_retry = 0; in r8712_set_rpwm()
54 r8712_write8(padapter, 0x1025FE58, rpwm); in r8712_set_rpwm()
55 pwrpriv->tog += 0x80; in r8712_set_rpwm()
66 smart_ps = 0; in r8712_set_ps_mode()
92 if (pwrpriv->cpwm_tog == ((preportpwrstate->state) & 0x80)) in r8712_cpwm_int_hdl()
96 pwrpriv->cpwm = (preportpwrstate->state) & 0xf; in r8712_cpwm_int_hdl()
101 pwrpriv->cpwm_tog = (preportpwrstate->state) & 0x80; in r8712_cpwm_int_hdl()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbif/
Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
Dnbif_6_3_1_offset.h28 // base address: 0x0
29 …IRQ_BRIDGE_CNTL 0x003e
33 // base address: 0x0
34 …BIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
35 …BIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
36 …BIF_CFG_DEV0_EPF0_COMMAND 0x0004
37 …BIF_CFG_DEV0_EPF0_STATUS 0x0006
38 …BIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
39 …BIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
40 …BIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
[all …]
/linux-6.12.1/arch/x86/pci/
Dolpc.c33 * the size of the region by writing ~0 to a base address register
38 * ~0 to a base address register.
41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
42 0x0, 0x0, 0x0, 0x0,
43 0x0, 0x0, 0x0, 0x0,
45 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
46 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
47 0x0, 0x0, 0x0, 0x28100b,
48 0x0, 0x0, 0x0, 0x0,
49 0x0, 0x0, 0x0, 0x0,
[all …]
/linux-6.12.1/arch/mips/ath25/
Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-au1x00/
Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]
/linux-6.12.1/sound/soc/codecs/
Drt1308.c32 { RT1308_I2C_I2S_SDW_SET, 0x01014005 },
33 { RT1308_CLASS_D_SET_2, 0x227f5501 },
34 { RT1308_PADS_1, 0x50150505 },
35 { RT1308_VREF, 0x18100000 },
36 { RT1308_IV_SENSE, 0x87010000 },
37 { RT1308_DUMMY_REG, 0x00000200 },
38 { RT1308_SIL_DET, 0xe1c30000 },
39 { RT1308_DC_CAL_2, 0x00ffff00 },
40 { RT1308_CLK_DET, 0x01000000 },
41 { RT1308_POWER_STATUS, 0x08800000 },
[all …]
/linux-6.12.1/drivers/ata/
Dpata_via.c70 VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */
71 VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */
72 VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */
73 VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */
74 VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */
75 VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
76 VIA_NO_ENABLES = 0x40, /* Has no enablebits */
77 VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */
81 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
96 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dste-nomadik-stn8815.dtsi14 reg = <0x00000000 0x04000000>,
15 <0x08000000 0x04000000>;
20 reg = <0x10210000 0x1000>;
37 reg = <0x101e2000 0x1000>;
46 reg = <0x101e3000 0x1000>;
55 reg = <0x101e4000 0x80>;
62 gpio-bank = <0>;
63 gpio-ranges = <&pinctrl 0 0 32>;
69 reg = <0x101e5000 0x80>;
77 gpio-ranges = <&pinctrl 0 32 32>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/tesla/
Dfsd.dtsi39 #size-cells = <0>;
88 /* Cluster 0 */
89 cpucl0_0: cpu@0 {
92 reg = <0x0 0x000>;
96 i-cache-size = <0xc000>;
99 d-cache-size = <0x8000>;
108 reg = <0x0 0x001>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
124 reg = <0x0 0x002>;
[all …]
/linux-6.12.1/arch/mips/alchemy/common/
Ddbdma.c68 { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
69 { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
70 { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
71 { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
74 { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
75 { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
76 { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
77 { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
80 { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
81 { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
[all …]
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]

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