32 	{ RT1308_I2C_I2S_SDW_SET,	0x01014005 },
33 	{ RT1308_CLASS_D_SET_2,		0x227f5501 },
34 	{ RT1308_PADS_1,		0x50150505 },
35 	{ RT1308_VREF,			0x18100000 },
36 	{ RT1308_IV_SENSE,		0x87010000 },
37 	{ RT1308_DUMMY_REG,		0x00000200 },
38 	{ RT1308_SIL_DET,		0xe1c30000 },
39 	{ RT1308_DC_CAL_2,		0x00ffff00 },
40 	{ RT1308_CLK_DET,		0x01000000 },
41 	{ RT1308_POWER_STATUS,		0x08800000 },
42 	{ RT1308_DAC_SET,		0xafaf0700 },
64 	{ 0x01, 0x1f3f5f00 },
65 	{ 0x02, 0x07000000 },
66 	{ 0x03, 0x80003e00 },
67 	{ 0x04, 0x80800600 },
68 	{ 0x05, 0x0aaa1a0a },
69 	{ 0x06, 0x52000000 },
70 	{ 0x07, 0x00000000 },
71 	{ 0x08, 0x00600000 },
72 	{ 0x09, 0xe1030000 },
73 	{ 0x0a, 0x00000000 },
74 	{ 0x0b, 0x30000000 },
75 	{ 0x0c, 0x7fff7000 },
76 	{ 0x10, 0xffff0700 },
77 	{ 0x11, 0x0a000000 },
78 	{ 0x12, 0x60040000 },
79 	{ 0x13, 0x00000000 },
80 	{ 0x14, 0x0f300000 },
81 	{ 0x15, 0x00000022 },
82 	{ 0x16, 0x02000000 },
83 	{ 0x17, 0x01004045 },
84 	{ 0x18, 0x00000000 },
85 	{ 0x19, 0x00000000 },
86 	{ 0x1a, 0x80000000 },
87 	{ 0x1b, 0x10325476 },
88 	{ 0x1c, 0x1d1d0000 },
89 	{ 0x20, 0xd2101300 },
90 	{ 0x21, 0xf3ffff00 },
91 	{ 0x22, 0x00000000 },
92 	{ 0x23, 0x00000000 },
93 	{ 0x24, 0x00000000 },
94 	{ 0x25, 0x00000000 },
95 	{ 0x26, 0x00000000 },
96 	{ 0x27, 0x00000000 },
97 	{ 0x28, 0x00000000 },
98 	{ 0x29, 0x00000000 },
99 	{ 0x2a, 0x00000000 },
100 	{ 0x2b, 0x00000000 },
101 	{ 0x2c, 0x00000000 },
102 	{ 0x2d, 0x00000000 },
103 	{ 0x2e, 0x00000000 },
104 	{ 0x2f, 0x00000000 },
105 	{ 0x30, 0x01000000 },
106 	{ 0x31, 0x20025501 },
107 	{ 0x32, 0x00000000 },
108 	{ 0x33, 0x105a0000 },
109 	{ 0x34, 0x10100000 },
110 	{ 0x35, 0x2aaa52aa },
111 	{ 0x36, 0x00c00000 },
112 	{ 0x37, 0x20046100 },
113 	{ 0x50, 0x10022f00 },
114 	{ 0x51, 0x003c0000 },
115 	{ 0x54, 0x04000000 },
116 	{ 0x55, 0x01000000 },
117 	{ 0x56, 0x02000000 },
118 	{ 0x57, 0x02000000 },
119 	{ 0x58, 0x02000000 },
120 	{ 0x59, 0x02000000 },
121 	{ 0x5b, 0x02000000 },
122 	{ 0x5c, 0x00000000 },
123 	{ 0x5d, 0x00000000 },
124 	{ 0x5e, 0x00000000 },
125 	{ 0x5f, 0x00000000 },
126 	{ 0x60, 0x02000000 },
127 	{ 0x61, 0x00000000 },
128 	{ 0x62, 0x00000000 },
129 	{ 0x63, 0x00000000 },
130 	{ 0x64, 0x00000000 },
131 	{ 0x65, 0x02000000 },
132 	{ 0x66, 0x00000000 },
133 	{ 0x67, 0x00000000 },
134 	{ 0x68, 0x00000000 },
135 	{ 0x69, 0x00000000 },
136 	{ 0x6a, 0x02000000 },
137 	{ 0x6c, 0x00000000 },
138 	{ 0x6d, 0x00000000 },
139 	{ 0x6e, 0x00000000 },
140 	{ 0x70, 0x10EC1308 },
141 	{ 0x71, 0x00000000 },
142 	{ 0x72, 0x00000000 },
143 	{ 0x73, 0x00000000 },
144 	{ 0x74, 0x00000000 },
145 	{ 0x75, 0x00000000 },
146 	{ 0x76, 0x00000000 },
147 	{ 0x77, 0x00000000 },
148 	{ 0x78, 0x00000000 },
149 	{ 0x79, 0x00000000 },
150 	{ 0x7a, 0x00000000 },
151 	{ 0x7b, 0x00000000 },
152 	{ 0x7c, 0x00000000 },
153 	{ 0x7d, 0x00000000 },
154 	{ 0x7e, 0x00000000 },
155 	{ 0x7f, 0x00020f00 },
156 	{ 0x80, 0x00000000 },
157 	{ 0x81, 0x00000000 },
158 	{ 0x82, 0x00000000 },
159 	{ 0x83, 0x00000000 },
160 	{ 0x84, 0x00000000 },
161 	{ 0x85, 0x00000000 },
162 	{ 0x86, 0x00000000 },
163 	{ 0x87, 0x00000000 },
164 	{ 0x88, 0x00000000 },
165 	{ 0x89, 0x00000000 },
166 	{ 0x8a, 0x00000000 },
167 	{ 0x8b, 0x00000000 },
168 	{ 0x8c, 0x00000000 },
169 	{ 0x8d, 0x00000000 },
170 	{ 0x8e, 0x00000000 },
171 	{ 0x90, 0x50250905 },
172 	{ 0x91, 0x15050000 },
173 	{ 0xa0, 0x00000000 },
174 	{ 0xa1, 0x00000000 },
175 	{ 0xa2, 0x00000000 },
176 	{ 0xa3, 0x00000000 },
177 	{ 0xa4, 0x00000000 },
178 	{ 0xb0, 0x00000000 },
179 	{ 0xb1, 0x00000000 },
180 	{ 0xb2, 0x00000000 },
181 	{ 0xb3, 0x00000000 },
182 	{ 0xb4, 0x00000000 },
183 	{ 0xb5, 0x00000000 },
184 	{ 0xb6, 0x00000000 },
185 	{ 0xb7, 0x00000000 },
186 	{ 0xb8, 0x00000000 },
187 	{ 0xb9, 0x00000000 },
188 	{ 0xba, 0x00000000 },
189 	{ 0xbb, 0x00000000 },
190 	{ 0xc0, 0x01000000 },
191 	{ 0xc1, 0x00000000 },
192 	{ 0xf0, 0x00000000 },
312 			RT1308_POW_PDB_REG_BIT | RT1308_POW_PDB_MN_BIT, 0);  in rt1308_classd_event()
320 	return 0;  in rt1308_classd_event()
349 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
353 		RT1308_POW_MBIAS20U_BIT, 0, NULL, 0),
355 		RT1308_POW_ALDO_BIT, 0, NULL, 0),
357 		RT1308_POW_DBG_BIT, 0, NULL, 0),
359 		RT1308_POW_DACL_BIT, 0, NULL, 0),
361 		RT1308_POW_CLK25M_BIT, 0, NULL, 0),
363 		RT1308_POW_ADC_R_BIT, 0, NULL, 0),
365 		RT1308_POW_ADC_L_BIT, 0, NULL, 0),
367 		RT1308_POW_DLDO_BIT, 0, NULL, 0),
369 		RT1308_POW_VREF_BIT, 0, NULL, 0),
371 		RT1308_POW_MIXER_R_BIT, 0, NULL, 0),
373 		RT1308_POW_MIXER_L_BIT, 0, NULL, 0),
375 		RT1308_POW_MBIAS4U_BIT, 0, NULL, 0),
377 		RT1308_POW_PLL2_LDO_EN_BIT, 0, NULL, 0),
379 		RT1308_POW_PLL2B_EN_BIT, 0, NULL, 0),
381 		RT1308_POW_PLL2F_EN_BIT, 0, NULL, 0),
383 		RT1308_POW_PLL2F2_EN_BIT, 0, NULL, 0),
385 		RT1308_POW_PLL2B2_EN_BIT, 0, NULL, 0),
389 		RT1308_POW_DAC1_BIT, 0, NULL, 0),
390 	SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
391 	SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
392 	SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
395 	SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
440 	if (sclk <= 0 || rate <= 0)  in rt1308_get_clk_info()
444 	for (i = 0; i < ARRAY_SIZE(pd); i++)  in rt1308_get_clk_info()
456 	unsigned int val_len = 0, val_clk, mask_clk;  in rt1308_hw_params()
461 	if (pre_div < 0) {  in rt1308_hw_params()
468 	if (frame_size < 0) {  in rt1308_hw_params()
516 	return 0;  in rt1308_hw_params()
523 	unsigned int reg_val = 0, reg1_val = 0;  in rt1308_set_dai_fmt()
527 		rt1308->master = 0;  in rt1308_set_dai_fmt()
572 	return 0;  in rt1308_set_dai_fmt()
579 	unsigned int reg_val = 0;  in rt1308_set_component_sysclk()
582 		return 0;  in rt1308_set_component_sysclk()
612 	return 0;  in rt1308_set_component_sysclk()
625 		return 0;  in rt1308_set_component_pll()
630 		rt1308->pll_in = 0;  in rt1308_set_component_pll()
631 		rt1308->pll_out = 0;  in rt1308_set_component_pll()
635 		return 0;  in rt1308_set_component_pll()
664 	if (ret < 0) {  in rt1308_set_component_pll()
670 		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),  in rt1308_set_component_pll()
676 		((pll_code.m_bp ? 0 : pll_code.m_code) << RT1308_PLL1_M_SFT) |  in rt1308_set_component_pll()
683 	return 0;  in rt1308_set_component_pll()
699 	regmap_write(rt1308->regmap, RT1308_RESET, 0);  in rt1308_remove()
710 	return 0;  in rt1308_suspend()
720 	return 0;  in rt1308_resume()
791 	{ "10EC1308", 0, },
805 	regmap_write(rt1308->regmap, RT1308_RESET, 0);  in rt1308_efuse()
807 	regmap_write(rt1308->regmap, RT1308_POWER_STATUS, 0x01800000);  in rt1308_efuse()
809 	regmap_write(rt1308->regmap, RT1308_EFUSE_1, 0x44fe0f00);  in rt1308_efuse()
811 	regmap_write(rt1308->regmap, RT1308_PVDD_OFFSET_CTL, 0x10000000);  in rt1308_efuse()
837 	if ((val & 0xFFFFFF00) != RT1308_DEVICE_ID_NUM) {  in rt1308_i2c_probe()
854 	regmap_write(rt1308->regmap, RT1308_RESET, 0);  in rt1308_i2c_shutdown()