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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dhisilicon-femac.txt32 reg = <0x10090000 0x1000>,<0x10091300 0x200>;
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dstarfive,jh7110-tdm.yaml64 const: 0
82 reg = <0x10090000 0x1000>;
97 #sound-dai-cells = <0>;
/linux-6.12.1/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
188 <&cpu0_intc 0xffffffff>,
189 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
190 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
191 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
59 reg = <0x1>;
86 reg = <0x2>;
113 reg = <0x3>;
140 reg = <0x4>;
184 #address-cells = <0>;
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
186 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a08g045.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
22 reg = <0>;
30 L3_CA55: cache-controller-0 {
34 cache-size = <0x40000>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
59 reg = <0 0x1004b800 0 0x400>;
77 reg = <0 0x10090000 0 0x400>;
93 #size-cells = <0>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3xxx.dtsi39 #clock-cells = <0>;
45 reg = <0x10090000 0x10000>;
56 reg = <0x10104000 0x800>;
68 reg = <0x10138000 0x1000>;
75 reg = <0x1013c000 0x100>;
80 reg = <0x1013c200 0x20>;
94 reg = <0x1013c600 0x20>;
103 reg = <0x1013d000 0x1000>,
104 <0x1013c100 0x0100>;
109 reg = <0x10124000 0x400>;
[all …]
Drk3036.dtsi37 #size-cells = <0>;
43 reg = <0xf00>;
56 reg = <0xf01>;
87 #clock-cells = <0>;
92 reg = <0x10080000 0x2000>;
95 ranges = <0 0x10080000 0x2000>;
97 smp-sram@0 {
99 reg = <0x00 0x10>;
105 reg = <0x10090000 0x10000>;
125 reg = <0x10108000 0x800>;
[all …]
Drk3128.dtsi44 #size-cells = <0>;
50 reg = <0xf00>;
61 reg = <0xf01>;
69 reg = <0xf02>;
77 reg = <0xf03>;
83 cpu_opp_table: opp-table-0 {
159 #clock-cells = <0>;
164 reg = <0x10080000 0x2000>;
167 ranges = <0 0x10080000 0x2000>;
169 smp-sram@0 {
[all …]
/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]