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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dmediatek,pericfg.yaml60 reg = <0x10003000 0x1000>;
68 reg = <0x10003000 0x1000>;
Dmediatek,mt8192-sys-clock.yaml45 reg = <0x10000000 0x1000>;
52 reg = <0x10001000 0x1000>;
59 reg = <0x10003000 0x1000>;
66 reg = <0x1000c000 0x1000>;
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dingenic,rtc.yaml54 const: 0
63 minimum: 0
71 minimum: 0
92 reg = <0x10003000 0x40>;
105 reg = <0x10003000 0x4c>;
113 #clock-cells = <0>;
/linux-6.12.1/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt7986-wed-pcie.yaml41 reg = <0 0x10003000 0 0x10>;
/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dfsl,imxgpt.yaml102 reg = <0x10003000 0x1000>;
/linux-6.12.1/arch/arm/boot/dts/hisilicon/
Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dinterrupts.txt17 interrupts = <5 0>, <6 0>;
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
55 reg = <0x10140000 0x1000>;
62 reg = <0x10003000 0x1000>;
72 - bits[3:0] trigger type and level flags
83 reg = <0x41>;
99 reg = <0x2b>;
102 interrupts = <3 0x8>;
105 #size-cells = <0>;
107 threshold = <0x40>;
/linux-6.12.1/arch/mips/include/asm/mach-ralink/
Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/linux-6.12.1/arch/arm64/boot/dts/sprd/
Dsc9836.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0x0 0x0>;
28 reg = <0x0 0x1>;
35 reg = <0x0 0x2>;
42 reg = <0x0 0x3>;
49 reg = <0 0x10003000 0 0x1000>;
63 reg = <0 0x10001000 0 0x1000>;
77 #size-cells = <0>;
79 port@0 {
[all …]
Dsc9863a.dtsi15 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
57 reg = <0x0 0x100>;
65 reg = <0x0 0x200>;
73 reg = <0x0 0x300>;
81 reg = <0x0 0x400>;
89 reg = <0x0 0x500>;
97 reg = <0x0 0x600>;
105 reg = <0x0 0x700>;
[all …]
Dsc9860.dtsi16 #size-cells = <0>;
53 reg = <0x0 0x530000>;
61 reg = <0x0 0x530001>;
69 reg = <0x0 0x530002>;
77 reg = <0x0 0x530003>;
85 reg = <0x0 0x530100>;
93 reg = <0x0 0x530101>;
101 reg = <0x0 0x530102>;
109 reg = <0x0 0x530103>;
124 arm,psci-suspend-param = <0x00010002>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt7981b.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0x0>;
26 reg = <0x1>;
36 #clock-cells = <0>;
52 reg = <0 0x0c000000 0 0x40000>, /* GICD */
53 <0 0x0c080000 0 0x200000>; /* GICR */
62 reg = <0 0x10001000 0 0x1000>;
68 reg = <0 0x1001b000 0 0x1000>;
74 reg = <0 0x1001c000 0 0x1000>;
[all …]
Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/wireless/
Dmediatek,mt76.yaml138 "^r[0-9]+":
159 "^b[0-9]+$":
247 wifi@0,0 {
249 reg = <0x0000 0 0 0 0>;
251 mediatek,mtd-eeprom = <&factory 0x8000>;
286 reg = <0x10300000 0x100000>;
300 reg = <0x10300000 0x100000>;
313 reg = <0x18000000 0x1000000>,
314 <0x10003000 0x1000>,
315 <0x11d10000 0x1000>;
/linux-6.12.1/arch/mips/boot/dts/ingenic/
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/linux-6.12.1/drivers/clk/imx/
Dclk-imx27.c15 #define MX27_CCM_BASE_ADDR 0x10027000
16 #define MX27_GPT1_BASE_ADDR 0x10003000
22 #define CCM_CSCR (ccm + 0x00)
23 #define CCM_MPCTL0 (ccm + 0x04)
24 #define CCM_MPCTL1 (ccm + 0x08)
25 #define CCM_SPCTL0 (ccm + 0x0c)
26 #define CCM_SPCTL1 (ccm + 0x10)
27 #define CCM_PCDR0 (ccm + 0x18)
28 #define CCM_PCDR1 (ccm + 0x1c)
29 #define CCM_PCCR0 (ccm + 0x20)
[all …]
/linux-6.12.1/arch/arm/boot/dts/arm/
Dversatile-ab.dts24 reg = <0x0 0x08000000>;
28 #clock-cells = <0>;
38 #size-cells = <0>;
40 port@0 {
41 reg = <0>;
71 reg = <0x10000000 0x200>;
72 ranges = <0x0 0x10000000 0x200>;
76 led@8,0 {
78 reg = <0x08 0x04>;
79 offset = <0x08>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]

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