clk/imx/clk-imx27.c

15 #define MX27_CCM_BASE_ADDR	0x10027000
16 #define MX27_GPT1_BASE_ADDR	0x10003000
22 #define CCM_CSCR		(ccm + 0x00)
23 #define CCM_MPCTL0		(ccm + 0x04)
24 #define CCM_MPCTL1		(ccm + 0x08)
25 #define CCM_SPCTL0		(ccm + 0x0c)
26 #define CCM_SPCTL1		(ccm + 0x10)
27 #define CCM_PCDR0		(ccm + 0x18)
28 #define CCM_PCDR1		(ccm + 0x1c)
29 #define CCM_PCCR0		(ccm + 0x20)
30 #define CCM_PCCR1		(ccm + 0x24)
31 #define CCM_CCSR		(ccm + 0x28)
55 	clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);  in _mx27_clocks_init()
76 	clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);  in _mx27_clocks_init()
78 	clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);  in _mx27_clocks_init()
86 …clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_s…  in _mx27_clocks_init()
98 	clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);  in _mx27_clocks_init()
99 	clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);  in _mx27_clocks_init()
187 	ccm = of_iomap(np, 0);  in mx27_clocks_init_dt()