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/linux-6.12.1/drivers/vfio/pci/hisilicon/
Dhisi_acc_vfio_pci.h11 #define QM_CACHE_WB_START 0x204
12 #define QM_CACHE_WB_DONE 0x208
13 #define QM_MB_CMD_PAUSE_QM 0xe
14 #define QM_ABNORMAL_INT_STATUS 0x100008
15 #define QM_IFC_INT_STATUS 0x0028
16 #define SEC_CORE_INT_STATUS 0x301008
17 #define HPRE_HAC_INT_STATUS 0x301800
18 #define HZIP_CORE_INT_STATUS 0x3010AC
20 #define QM_VFT_CFG_RDY 0x10006c
21 #define QM_VFT_CFG_OP_WR 0x100058
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dst,stm32-qspi.yaml69 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
72 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
73 <&mdma1 22 0x10 0x100008 0x0 0x0>;
79 #size-cells = <0>;
81 flash@0 {
83 reg = <0>;
/linux-6.12.1/arch/m68k/include/asm/
Dm527xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
Dm523xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb/
Delmer0.h39 #define A_ELMER0_VERSION 0x100000
40 #define A_ELMER0_PHY_CFG 0x100004
41 #define A_ELMER0_INT_ENABLE 0x100008
42 #define A_ELMER0_INT_CAUSE 0x10000c
43 #define A_ELMER0_GPI_CFG 0x100010
44 #define A_ELMER0_GPI_STAT 0x100014
45 #define A_ELMER0_GPO 0x100018
46 #define A_ELMER0_PORT0_MI1_CFG 0x400000
48 #define S_MI1_MDI_ENABLE 0
61 #define M_MI1_SOF 0x3
[all …]
/linux-6.12.1/drivers/video/fbdev/
Dplatinumfb.c123 int err, offset = 0x20; in platinumfb_set_par()
125 if((err = platinum_var_to_par(&info->var, pinfo, 0))) { in platinumfb_set_par()
136 offset = 0x10; in platinumfb_set_par()
147 return 0; in platinumfb_set_par()
153 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL in platinumfb_blank()
155 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due in platinumfb_blank()
167 ctrl = le32_to_cpup(&info->platinum_regs->ctrl.r) | 0x33; in platinumfb_blank()
173 ctrl &= ~0x30; in platinumfb_blank()
177 return 0; in platinumfb_blank()
216 return 0; in platinumfb_setcolreg()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/umc/
Dumc_6_7_0_offset.h29 // base address: 0x50f00
30 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
31 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
32 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
33 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
34 …MCA_UMC_UMC0_MCUMC_MISC0T0 0x03c6
35 …e regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 0
36 …MCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca
37 …e regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 0
38 …MCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc
[all …]
/linux-6.12.1/drivers/media/pci/cx25821/
Dcx25821-reg.h13 #define RISC_CNT_INC 0x00010000
14 #define RISC_CNT_RESET 0x00030000
15 #define RISC_IRQ1 0x01000000
16 #define RISC_IRQ2 0x02000000
17 #define RISC_EOL 0x04000000
18 #define RISC_SOL 0x08000000
19 #define RISC_WRITE 0x10000000
20 #define RISC_SKIP 0x20000000
21 #define RISC_JUMP 0x70000000
22 #define RISC_SYNC 0x80000000
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/linux-6.12.1/drivers/crypto/hisilicon/
Dqm.c21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
26 #define QM_IRQ_VECTOR_MASK GENMASK(15, 0)
27 #define QM_IRQ_TYPE_MASK GENMASK(15, 0)
29 #define QM_ABN_IRQ_TYPE_MASK GENMASK(7, 0)
32 #define QM_MB_PING_ALL_VFS 0xffff
34 #define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
38 #define QM_SQ_HOP_NUM_SHIFT 0
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