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/linux-6.12.1/drivers/media/pci/mgb4/
Dmgb4_cmt.c19 …{0x1208, 0x0000, 0x171C, 0x0000, 0x1E38, 0x0000, 0x11C7, 0x0000, 0x1041, 0x01BC, 0x7C01, 0x7DE9, 0…
20 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x130D, 0x0080, 0x0041, 0x0090, 0x7C01, 0x7DE9, 0…
21 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x165A, 0x0080, 0x0082, 0x00FA, 0x7C01, 0x7DE9, 0…
22 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x1187, 0x0080, 0x1041, 0x01EE, 0x7C01, 0x7DE9, 0…
23 …{0x1186, 0x0000, 0x1555, 0x0000, 0x1AAA, 0x0000, 0x1451, 0x0000, 0x0042, 0x0013, 0x7C01, 0x7DE9, 0…
24 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x134E, 0x0080, 0x0041, 0x005E, 0x7C01, 0x7DE9, 0…
25 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x1619, 0x0080, 0x0083, 0x00FA, 0x7C01, 0x7DE9, 0…
26 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x179E, 0x0000, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
27 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x179F, 0x0080, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
28 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x17DF, 0x0000, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
Dclk-exynos7.c13 /* Register Offset definitions for CMU_TOPC (0x10570000) */
14 #define CC_PLL_LOCK 0x0000
15 #define BUS0_PLL_LOCK 0x0004
16 #define BUS1_DPLL_LOCK 0x0008
17 #define MFC_PLL_LOCK 0x000C
18 #define AUD_PLL_LOCK 0x0010
19 #define CC_PLL_CON0 0x0100
20 #define BUS0_PLL_CON0 0x0110
21 #define BUS1_DPLL_CON0 0x0120
22 #define MFC_PLL_CON0 0x0130
[all …]
Dclk-exynos5433.c50 #define ISP_PLL_LOCK 0x0000
51 #define AUD_PLL_LOCK 0x0004
52 #define ISP_PLL_CON0 0x0100
53 #define ISP_PLL_CON1 0x0104
54 #define ISP_PLL_FREQ_DET 0x0108
55 #define AUD_PLL_CON0 0x0110
56 #define AUD_PLL_CON1 0x0114
57 #define AUD_PLL_CON2 0x0118
58 #define AUD_PLL_FREQ_DET 0x011c
59 #define MUX_SEL_TOP0 0x0200
[all …]
/linux-6.12.1/include/pcmcia/
Dciscode.h17 #define MANFID_3COM 0x0101
18 #define PRODID_3COM_3CXEM556 0x0035
19 #define PRODID_3COM_3CCFEM556 0x0556
20 #define PRODID_3COM_3C562 0x0562
22 #define MANFID_ACCTON 0x01bf
23 #define PRODID_ACCTON_EN2226 0x010a
25 #define MANFID_ADAPTEC 0x012f
26 #define PRODID_ADAPTEC_SCSI 0x0001
28 #define MANFID_ATT 0xffff
29 #define PRODID_ATT_KIT 0x0100
[all …]
/linux-6.12.1/drivers/media/i2c/
Dimx355.c14 #define IMX355_REG_MODE_SELECT 0x0100
15 #define IMX355_MODE_STANDBY 0x00
16 #define IMX355_MODE_STREAMING 0x01
19 #define IMX355_REG_CHIP_ID 0x0016
20 #define IMX355_CHIP_ID 0x0355
23 #define IMX355_REG_FLL 0x0340
24 #define IMX355_FLL_MAX 0xffff
27 #define IMX355_REG_EXPOSURE 0x0202
30 #define IMX355_EXPOSURE_DEFAULT 0x0282
33 #define IMX355_REG_ANALOG_GAIN 0x0204
[all …]
Dhi847.c25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
[all …]
/linux-6.12.1/arch/x86/boot/
Dvideo.h25 * of compatibility when extending the table. These are between 0x00 and 0xff.
27 #define VIDEO_FIRST_MENU 0x0000
29 /* Standard BIOS video modes (BIOS number + 0x0100) */
30 #define VIDEO_FIRST_BIOS 0x0100
32 /* VESA BIOS video modes (VESA number + 0x0200) */
33 #define VIDEO_FIRST_VESA 0x0200
35 /* Video7 special modes (BIOS number + 0x0900) */
36 #define VIDEO_FIRST_V7 0x0900
39 #define VIDEO_FIRST_SPECIAL 0x0f00
40 #define VIDEO_80x25 0x0f00
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dcm81xx.h13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
25 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
26 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
/linux-6.12.1/drivers/net/fddi/skfp/h/
Dfplustm.h113 #define VOID_FRAME_OFF 0x00
114 #define CLAIM_FRAME_OFF 0x08
115 #define BEACON_FRAME_OFF 0x10
116 #define DBEACON_FRAME_OFF 0x18
117 #define RX_FIFO_OFF 0x21 /* to get a prime number for */
120 #define RBC_MEM_SIZE 0x8000
121 #define SEND_ASYNC_AS_SYNC 0x1
122 #define SYNC_TRAFFIC_ON 0x2
125 #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
126 #define TX_FIFO_SPACE 0x4000
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Ddra72x.dtsi27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/linux-6.12.1/drivers/usb/serial/
Dnavman.c21 { USB_DEVICE(0x0a99, 0x0001) }, /* Talon Technology device */
22 { USB_DEVICE(0x0df7, 0x0900) }, /* Mobile Action i-gotU */
35 case 0: in navman_read_int_callback()
68 int result = 0; in navman_open()
/linux-6.12.1/drivers/gpio/
Dgpio-mxs.c22 #define MXS_SET 0x4
23 #define MXS_CLR 0x8
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/abi/
Dguc_klvs_abi.h17 * | 0 | 31:16 | **KEY** - KLV key identifier |
23 * | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) |
25 * | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) |
29 * | n | 31:0 | |
34 #define GUC_KLV_0_KEY (0xffffu << 16)
35 #define GUC_KLV_0_LEN (0xffffu << 0)
36 #define GUC_KLV_n_VALUE (0xffffffffu << 0)
43 * _`GUC_KLV_GLOBAL_CFG_GMD_ID` : 0x3000
49 #define GUC_KLV_GLOBAL_CFG_GMD_ID_KEY 0x3000u
57 * _`GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR` : 0x0900
[all …]
/linux-6.12.1/drivers/net/dsa/mv88e6xxx/
Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/linux-6.12.1/drivers/tty/serial/
Ddz.h18 #define DZ_TRDY 0x8000 /* Transmitter empty */
19 #define DZ_TIE 0x4000 /* Transmitter Interrupt Enbl */
20 #define DZ_TLINE 0x0300 /* Transmitter Line Number */
21 #define DZ_RDONE 0x0080 /* Receiver data ready */
22 #define DZ_RIE 0x0040 /* Receive Interrupt Enable */
23 #define DZ_MSE 0x0020 /* Master Scan Enable */
24 #define DZ_CLR 0x0010 /* Master reset */
25 #define DZ_MAINT 0x0008 /* Loop Back Mode */
30 #define DZ_RBUF_MASK 0x00FF /* Data Mask */
31 #define DZ_LINE_MASK 0x0300 /* Line Mask */
[all …]
/linux-6.12.1/drivers/net/wireless/intersil/p54/
Deeprom.h131 /* common and choice range (0x0000 - 0x0fff) */
132 #define PDR_END 0x0000
133 #define PDR_MANUFACTURING_PART_NUMBER 0x0001
134 #define PDR_PDA_VERSION 0x0002
135 #define PDR_NIC_SERIAL_NUMBER 0x0003
136 #define PDR_NIC_RAM_SIZE 0x0005
137 #define PDR_RFMODEM_SUP_RANGE 0x0006
138 #define PDR_PRISM_MAC_SUP_RANGE 0x0007
139 #define PDR_NIC_ID 0x0008
141 #define PDR_MAC_ADDRESS 0x0101
[all …]
/linux-6.12.1/arch/arm/include/asm/hardware/
Dcache-l2x0.h15 #define L2X0_CACHE_ID 0x000
16 #define L2X0_CACHE_TYPE 0x004
17 #define L2X0_CTRL 0x100
18 #define L2X0_AUX_CTRL 0x104
19 #define L310_TAG_LATENCY_CTRL 0x108
20 #define L310_DATA_LATENCY_CTRL 0x10C
21 #define L2X0_EVENT_CNT_CTRL 0x200
22 #define L2X0_EVENT_CNT1_CFG 0x204
23 #define L2X0_EVENT_CNT0_CFG 0x208
24 #define L2X0_EVENT_CNT1_VAL 0x20C
[all …]
/linux-6.12.1/include/linux/platform_data/
Dsh_mmcif.h31 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
36 #define MMCIF_CE_CMD_SET 0x00000000
37 #define MMCIF_CE_ARG 0x00000008
38 #define MMCIF_CE_ARG_CMD12 0x0000000C
39 #define MMCIF_CE_CMD_CTRL 0x00000010
40 #define MMCIF_CE_BLOCK_SET 0x00000014
41 #define MMCIF_CE_CLK_CTRL 0x00000018
42 #define MMCIF_CE_BUF_ACC 0x0000001C
43 #define MMCIF_CE_RESP3 0x00000020
44 #define MMCIF_CE_RESP2 0x00000024
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]

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