Lines Matching +full:0 +full:x0900
15 #define L2X0_CACHE_ID 0x000
16 #define L2X0_CACHE_TYPE 0x004
17 #define L2X0_CTRL 0x100
18 #define L2X0_AUX_CTRL 0x104
19 #define L310_TAG_LATENCY_CTRL 0x108
20 #define L310_DATA_LATENCY_CTRL 0x10C
21 #define L2X0_EVENT_CNT_CTRL 0x200
22 #define L2X0_EVENT_CNT1_CFG 0x204
23 #define L2X0_EVENT_CNT0_CFG 0x208
24 #define L2X0_EVENT_CNT1_VAL 0x20C
25 #define L2X0_EVENT_CNT0_VAL 0x210
26 #define L2X0_INTR_MASK 0x214
27 #define L2X0_MASKED_INTR_STAT 0x218
28 #define L2X0_RAW_INTR_STAT 0x21C
29 #define L2X0_INTR_CLEAR 0x220
30 #define L2X0_CACHE_SYNC 0x730
31 #define L2X0_DUMMY_REG 0x740
32 #define L2X0_INV_LINE_PA 0x770
33 #define L2X0_INV_WAY 0x77C
34 #define L2X0_CLEAN_LINE_PA 0x7B0
35 #define L2X0_CLEAN_LINE_IDX 0x7B8
36 #define L2X0_CLEAN_WAY 0x7BC
37 #define L2X0_CLEAN_INV_LINE_PA 0x7F0
38 #define L2X0_CLEAN_INV_LINE_IDX 0x7F8
39 #define L2X0_CLEAN_INV_WAY 0x7FC
42 * D and one I lockdown register at 0x0900 and 0x0904.
44 #define L2X0_LOCKDOWN_WAY_D_BASE 0x900
45 #define L2X0_LOCKDOWN_WAY_I_BASE 0x904
46 #define L2X0_LOCKDOWN_STRIDE 0x08
47 #define L310_ADDR_FILTER_START 0xC00
48 #define L310_ADDR_FILTER_END 0xC04
49 #define L2X0_TEST_OPERATION 0xF00
50 #define L2X0_LINE_DATA 0xF10
51 #define L2X0_LINE_TAG 0xF30
52 #define L2X0_DEBUG_CTRL 0xF40
53 #define L310_PREFETCH_CTRL 0xF60
54 #define L310_POWER_CTRL 0xF80
56 #define L310_STNDBY_MODE_EN (1 << 0)
59 #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
63 #define L2X0_CACHE_ID_RTL_MASK 0x3f
64 #define L210_CACHE_ID_RTL_R0P2_02 0x00
65 #define L210_CACHE_ID_RTL_R0P1 0x01
66 #define L210_CACHE_ID_RTL_R0P2_01 0x02
67 #define L210_CACHE_ID_RTL_R0P3 0x03
68 #define L210_CACHE_ID_RTL_R0P4 0x0b
69 #define L210_CACHE_ID_RTL_R0P5 0x0f
70 #define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
71 #define L310_CACHE_ID_RTL_R0P0 0x00
72 #define L310_CACHE_ID_RTL_R1P0 0x02
73 #define L310_CACHE_ID_RTL_R2P0 0x04
74 #define L310_CACHE_ID_RTL_R3P0 0x05
75 #define L310_CACHE_ID_RTL_R3P1 0x06
76 #define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
77 #define L310_CACHE_ID_RTL_R3P2 0x08
78 #define L310_CACHE_ID_RTL_R3P3 0x09
80 #define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0)
83 #define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf
84 #define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0
85 #define L2X0_EVENT_CNT_CFG_INT_DISABLED 0
97 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
98 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
118 #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
132 #define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
138 #define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f