/linux-6.12.1/arch/xtensa/boot/dts/ ! |
D | xtfpga-flash-128m.dtsi | 8 reg = <0x00000000 0x08000000>; 11 partition@0 { 13 reg = <0x00000000 0x06000000>; 17 reg = <0x06000000 0x00800000>; 21 reg = <0x06800000 0x017e0000>; 25 reg = <0x07fe0000 0x00020000>;
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D | lx200mx.dts | 8 memory@0 { 10 reg = <0x00000000 0x06000000>;
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D | xtfpga.dtsi | 9 …bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root… 12 memory@0 { 14 reg = <0x00000000 0x06000000>; 19 #size-cells = <0>; 20 cpu@0 { 22 reg = <0>; 30 * two cells: second cell == 0: internal irq number 39 #clock-cells = <0>; 49 ranges = <0x00000000 0xf0000000 0x10000000>; 52 #clock-cells = <0>; [all …]
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/linux-6.12.1/arch/sh/include/mach-common/mach/ ! |
D | sh7785lcr.h | 11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C 14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB 18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 23 #define NOR_FLASH_ADDR 0x00000000 [all …]
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/linux-6.12.1/arch/sh/boards/ ! |
D | board-urquell.c | 32 * SW2 0x1x xxxx -> little endian 39 * 0x00000000 - 0x04000000 (CS0) Nor Flash 40 * 0x04000000 - 0x04200000 (CS1) SRAM 41 * 0x05000000 - 0x05800000 (CS1) on board register 42 * 0x05800000 - 0x06000000 (CS1) LAN91C111 43 * 0x06000000 - 0x06400000 (CS1) PCMCIA 44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 45 * 0x10000000 - 0x14000000 (CS4) PCIe 46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM 47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM [all …]
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/linux-6.12.1/arch/arm/boot/dts/st/ ! |
D | ste-db8520.dtsi | 8 operating-points = <1152000 0 9 798720 0 10 399360 0 11 199680 0>; 22 reg = <0x06000000 0x00f00000>; 28 reg = <0x06f00000 0x00100000>; 34 reg = <0x07000000 0x01000000>; 48 reg = <0x17f00000 0x00100000>;
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D | ste-db8500.dtsi | 8 operating-points = <998400 0 9 798720 0 10 399360 0 11 199680 0>; 22 reg = <0x06000000 0x00f00000>; 28 reg = <0x06f00000 0x00100000>; 34 reg = <0x07000000 0x01000000>; 48 reg = <0x17f00000 0x00100000>;
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/linux-6.12.1/drivers/net/ethernet/intel/i40e/ ! |
D | i40e_debug.h | 11 I40E_DEBUG_INIT = 0x00000001, 12 I40E_DEBUG_RELEASE = 0x00000002, 14 I40E_DEBUG_LINK = 0x00000010, 15 I40E_DEBUG_PHY = 0x00000020, 16 I40E_DEBUG_HMC = 0x00000040, 17 I40E_DEBUG_NVM = 0x00000080, 18 I40E_DEBUG_LAN = 0x00000100, 19 I40E_DEBUG_FLOW = 0x00000200, 20 I40E_DEBUG_DCB = 0x00000400, 21 I40E_DEBUG_DIAG = 0x00000800, [all …]
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/linux-6.12.1/arch/arm64/boot/dts/ti/ ! |
D | k3-j721e.dtsi | 25 #size-cells = <0>; 39 cpu0: cpu@0 { 41 reg = <0x000>; 44 i-cache-size = <0xC000>; 47 d-cache-size = <0x8000>; 55 reg = <0x001>; 58 i-cache-size = <0xC000>; 61 d-cache-size = <0x8000>; 72 cache-size = <0x100000>; 114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ [all …]
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/linux-6.12.1/drivers/net/ethernet/ibm/emac/ ! |
D | tah.h | 52 #define TAH_MR_CVR 0x80000000 53 #define TAH_MR_SR 0x40000000 54 #define TAH_MR_ST_256 0x01000000 55 #define TAH_MR_ST_512 0x02000000 56 #define TAH_MR_ST_768 0x03000000 57 #define TAH_MR_ST_1024 0x04000000 58 #define TAH_MR_ST_1280 0x05000000 59 #define TAH_MR_ST_1536 0x06000000 60 #define TAH_MR_TFS_16KB 0x00000000 61 #define TAH_MR_TFS_2KB 0x00200000 [all …]
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/linux-6.12.1/arch/powerpc/include/asm/ ! |
D | reg_8xx.h | 29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */ 30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */ 38 #define LCTRL1_CTE_GT 0xc0000000 39 #define LCTRL1_CTF_LT 0x14000000 40 #define LCTRL1_CRWE_RW 0x00000000 41 #define LCTRL1_CRWE_RO 0x00040000 42 #define LCTRL1_CRWE_WO 0x000c0000 43 #define LCTRL1_CRWF_RW 0x00000000 44 #define LCTRL1_CRWF_RO 0x00010000 45 #define LCTRL1_CRWF_WO 0x00030000 [all …]
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/linux-6.12.1/arch/mips/boot/dts/brcm/ ! |
D | bcm3384_viper.dtsi | 7 memory@0 { 11 reg = <0x06000000 0x02000000>, 12 <0x0e000000 0x02000000>; 17 #size-cells = <0>; 22 cpu@0 { 25 reg = <0>; 30 #address-cells = <0>; 40 #clock-cells = <0>; 59 reg = <0x14e00048 0x4 0x14e0004c 0x4>, 60 <0x14e00350 0x4 0x14e00354 0x4>; [all …]
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/linux-6.12.1/drivers/net/wireless/ralink/rt2x00/ ! |
D | rt2800usb.h | 25 #define FIRMWARE_IMAGE_BASE 0x3000 39 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI 41 * 0:MGMT, 1:HCCA 2:EDCA 46 #define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff) 47 #define TXINFO_W0_WIV FIELD32(0x01000000) 48 #define TXINFO_W0_QSEL FIELD32(0x06000000) 49 #define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000) 50 #define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000) 51 #define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000) 58 * Word 0 [all …]
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D | rt2800mmio.h | 23 #define TX_QUEUE_REG_OFFSET 0x10 42 #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) 47 #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) 48 #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) 49 #define TXD_W1_BURST FIELD32(0x00008000) 50 #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) 51 #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) 52 #define TXD_W1_DMA_DONE FIELD32(0x80000000) 57 #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) 61 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI [all …]
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/linux-6.12.1/arch/mips/include/asm/mach-rc32434/ ! |
D | ddr.h | 49 #define DDR0_PHYS_ADDR 0x18018000 52 #define DDR_MASK 0xffff0000 58 #define RC32434_DDR0_ATA_MSK 0x000000E0 60 #define RC32434_DDR0_DBW_MSK 0x00000100 62 #define RC32434_DDR0_WR_MSK 0x00000600 64 #define RC32434_DDR0_PS_MSK 0x00001800 66 #define RC32434_DDR0_DTYPE_MSK 0x0000e000 68 #define RC32434_DDR0_RFC_MSK 0x000f0000 70 #define RC32434_DDR0_RP_MSK 0x00300000 72 #define RC32434_DDR0_AP_MSK 0x00400000 [all …]
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/linux-6.12.1/arch/powerpc/platforms/85xx/ ! |
D | p1022_rdk.c | 33 #define CLKDVDR_PXCKEN 0x80000000 34 #define CLKDVDR_PXCKINV 0x10000000 35 #define CLKDVDR_PXCKDLY 0x06000000 36 #define CLKDVDR_PXCLK_MASK 0x00FF0000 58 guts = of_iomap(guts_np, 0); in p1022rdk_set_pixel_clock() 101 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | in p1022_rdk_pic_init() 103 0, 256, " OpenPIC "); in p1022_rdk_pic_init() 114 ppc_md.progress("p1022_rdk_setup_arch()", 0); in p1022_rdk_setup_arch()
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/linux-6.12.1/sound/soc/fsl/ ! |
D | fsl_dma.h | 10 u8 res0[0x100]; 30 u8 res2[0x38]; 35 #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000 37 #define CCSR_DMA_MR_BWC_MASK 0x0F000000 40 #define CCSR_DMA_MR_EMP_EN 0x00200000 41 #define CCSR_DMA_MR_EMS_EN 0x00040000 42 #define CCSR_DMA_MR_DAHTS_MASK 0x00030000 43 #define CCSR_DMA_MR_DAHTS_1 0x00000000 44 #define CCSR_DMA_MR_DAHTS_2 0x00010000 45 #define CCSR_DMA_MR_DAHTS_4 0x00020000 [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ ! |
D | exynos-srom.yaml | 35 <bank-number> 0 <parent address of bank> <size> 39 "^.*@[0-3],[a-f0-9]+$": 53 typically 0 as this is the start of the bank. 77 Tacp: Page mode access cycle at Page mode (0 - 15) 78 Tcah: Address holding time after CSn (0 - 15) 79 Tcoh: Chip selection hold on OEn (0 - 15) 80 Tacc: Access cycle (0 - 31, the actual time is N + 1) 81 Tcos: Chip selection set-up before OEn (0 - 15) 82 Tacs: Address set-up before CSn (0 - 15) 99 reg = <0x12560000 0x14>; [all …]
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ ! |
D | gk104.c | 36 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_() 37 nvkm_wr32(device, 0x00c808, 0x00000000); in magic_() 38 nvkm_wr32(device, 0x00c800, ctrl); in magic_() 40 if (nvkm_rd32(device, 0x00c800) & 0x40000000) { in magic_() 42 nvkm_wr32(device, 0x00c804, 0x00000000); in magic_() 46 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_() 52 magic_(device, 0x8000a41f | ctrl, 6); in magic() 53 magic_(device, 0x80000421 | ctrl, 1); in magic() 61 if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001)) in gk104_pmu_pgob() 64 nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); in gk104_pmu_pgob() [all …]
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/linux-6.12.1/arch/mips/boot/dts/mobileye/ ! |
D | eyeq5.dtsi | 15 #size-cells = <0>; 16 cpu@0 { 19 reg = <0>; 34 reg = <0x8 0x04000000 0x0 0x1000000>; 37 reg = <0x8 0x05000000 0x0 0x1000000>; 40 reg = <0x8 0x06000000 0x0 0x100000>; 43 reg = <0x8 0x06100000 0x0 0x100000>; 47 reg = <0x8 0x06200000 0x0 0x100000>; 49 mhm_reserved_0: the-mhm-reserved-0@0 { 50 reg = <0x8 0x00000000 0x0 0x0000800>; [all …]
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/linux-6.12.1/drivers/net/wireless/realtek/rtw89/ ! |
D | rtw8852a_rfk_table.c | 8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001), 9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002), 10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001), 11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002), 12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005), 13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005), 14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005), 15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005), 16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), 17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), [all …]
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/linux-6.12.1/drivers/net/ethernet/engleder/ ! |
D | tsnep_hw.h | 12 #define ECM_TYPE 0x0000 13 #define ECM_REVISION_MASK 0x000000FF 14 #define ECM_REVISION_SHIFT 0 15 #define ECM_VERSION_MASK 0x0000FF00 17 #define ECM_QUEUE_COUNT_MASK 0x00070000 19 #define ECM_GATE_CONTROL 0x02000000 22 #define ECM_SYSTEM_TIME_LOW 0x0008 23 #define ECM_SYSTEM_TIME_HIGH 0x000C 26 #define ECM_CLOCK_RATE 0x0010 27 #define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF [all …]
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/linux-6.12.1/lib/ ! |
D | bitfield_kunit.c | 17 "u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \ 22 } while (0) 31 "le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\ 37 } while (0) 46 "be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \ 52 } while (0) 58 } while (0) 68 CHECK_ENC_GET(16, 1, 0x000f, 0x0001); in test_bitfields_constants() 69 CHECK_ENC_GET(16, 3, 0x00f0, 0x0030); in test_bitfields_constants() 70 CHECK_ENC_GET(16, 5, 0x0f00, 0x0500); in test_bitfields_constants() [all …]
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/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt76x2/ ! |
D | usb_mac.c | 11 s8 offset = 0; in mt76x2u_mac_fixup_xtal() 16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal() 17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal() 18 offset = 0; in mt76x2u_mac_fixup_xtal() 19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal() 20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal() 23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal() 25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal() 27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal() 28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal() [all …]
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/linux-6.12.1/arch/m68k/include/asm/ ! |
D | m54xxacr.h | 12 #define CACR_DEC 0x80000000 /* Enable data cache */ 13 #define CACR_DWP 0x40000000 /* Data write protection */ 14 #define CACR_DESB 0x20000000 /* Enable data store buffer */ 15 #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ 16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 18 #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 19 #define CACR_DDCM_P 0x04000000 /* No cache, precise */ 20 #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 21 #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ [all …]
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