Lines Matching +full:0 +full:x06000000

49 #define DDR0_PHYS_ADDR		0x18018000
52 #define DDR_MASK		0xffff0000
58 #define RC32434_DDR0_ATA_MSK		0x000000E0
60 #define RC32434_DDR0_DBW_MSK		0x00000100
62 #define RC32434_DDR0_WR_MSK		0x00000600
64 #define RC32434_DDR0_PS_MSK		0x00001800
66 #define RC32434_DDR0_DTYPE_MSK		0x0000e000
68 #define RC32434_DDR0_RFC_MSK		0x000f0000
70 #define RC32434_DDR0_RP_MSK		0x00300000
72 #define RC32434_DDR0_AP_MSK		0x00400000
74 #define RC32434_DDR0_RCD_MSK		0x01800000
76 #define RC32434_DDR0_CL_MSK		0x06000000
78 #define RC32434_DDR0_DBM_MSK		0x08000000
80 #define RC32434_DDR0_SDS_MSK		0x10000000
82 #define RC32434_DDR0_ATP_MSK		0x60000000
84 #define RC32434_DDR0_RE_MSK		0x80000000
88 #define RC32434_DDRC_CES_BIT		0
93 #define RC32434_DCST_CS_BIT		0
94 #define RC32434_DCST_CS_MSK		0x00000003
100 #define RC32434_DSCT_BA_MSK		0x000000c0
103 #define RC32434_QSC_DM_BIT		0
104 #define RC32434_QSC_DM_MSK		0x00000003
106 #define RC32434_QSC_DQSBS_MSK		0x000000fc
108 #define RC32434_QSC_DB_MSK		0x00000100
110 #define RC32434_QSC_DBSP_MSK		0x01fffe00
112 #define RC32434_QSC_BDP_MSK		0x7e000000
115 #define RC32434_LLC_EAO_BIT		0
116 #define RC32434_LLC_EAO_MSK		0x00000001
118 #define RC32434_LLC_EO_MSK		0x0000003e
120 #define RC32434_LLC_FS_MSK		0x000000c0
122 #define RC32434_LLC_AS_MSK		0x00000700
124 #define RC32434_LLC_SP_MSK		0x001ff800
128 #define RC32434_LLFC_MEN_BIT		0
134 #define RC32434_DLLTA_ADDR_MSK		0xfffffffc
138 #define RC32434_DLLED_DBE_BIT		0