| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-qserdes-txrx-v3.h | 10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
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| D | phy-qcom-qmp-qserdes-txrx.h | 10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
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| D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
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| D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
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| D | phy-qcom-qmp-pcs-sgmii.h | 9 #define QPHY_PCS_PHY_START 0x000
10 #define QPHY_PCS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_PCS_SW_RESET 0x008
12 #define QPHY_PCS_LINE_RESET_TIME 0x00c
13 #define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
14 #define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
15 #define QPHY_PCS_PCS_READY_STATUS 0x094
16 #define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
17 #define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
18 #define QPHY_PCS_SGMII_MISC_CTRL8 0x118
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| D | phy-qcom-qmp-pcs-usb-v5.h | 10 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
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| D | phy-qcom-qmp-pcs-usb-v4.h | 10 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
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| D | phy-qcom-qmp-pcs-v2.h | 10 #define QPHY_V2_PCS_SW_RESET 0x000
11 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_START_CONTROL 0x008
13 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
14 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
15 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
16 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
17 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
18 #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
19 #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
[all …]
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| D | phy-qcom-qmp-dp-phy.h | 10 #define QSERDES_DP_PHY_REVISION_ID0 0x000
11 #define QSERDES_DP_PHY_REVISION_ID1 0x004
12 #define QSERDES_DP_PHY_REVISION_ID2 0x008
13 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
14 #define QSERDES_DP_PHY_CFG 0x010
15 #define QSERDES_DP_PHY_CFG_1 0x014
16 #define QSERDES_DP_PHY_PD_CTL 0x018
17 #define QSERDES_DP_PHY_MODE 0x01c
18 #define QSERDES_DP_PHY_AUX_CFG0 0x020
19 #define QSERDES_DP_PHY_AUX_CFG1 0x024
[all …]
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| D | phy-qcom-qmp-qserdes-pll.h | 10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_EN_CENTER 0x010
12 #define QSERDES_PLL_SSC_ADJ_PER1 0x014
13 #define QSERDES_PLL_SSC_ADJ_PER2 0x018
14 #define QSERDES_PLL_SSC_PER1 0x01c
15 #define QSERDES_PLL_SSC_PER2 0x020
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
18 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
19 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
[all …]
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 176 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
178 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
180 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
182 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
185 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
187 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
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| D | clk-mt7981-topckgen.c | 293 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
295 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
297 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
299 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
302 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
304 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
306 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
308 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
309 0x1C0, 7),
312 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
[all …]
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| D | clk-mt7988-topckgen.c | 107 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
108 0, 2, 7, 0x1c0, 0),
109 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
110 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
111 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
112 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
114 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
116 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
117 0x018, 0, 1, 7, 0x1C0, 4),
[all …]
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| /linux-6.12.1/drivers/gpu/drm/vc4/ |
| D | vc4_hdmi_regs.h | 8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
166 VC4_HD_REG(HDMI_M_CTL, 0x000c),
167 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
168 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
169 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
170 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
171 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
172 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
173 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/hisilicon/ |
| D | hikey970-pinctrl.dtsi | 16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
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| /linux-6.12.1/drivers/video/fbdev/via/ |
| D | accel.h | 14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-driver-jz4780-efuse | 10 0x000 64 bit Random Number
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
13 0x028 3520 bit Reserved
14 0x1E0 8 bit Protect Segment
15 0x1E1 2296 bit HDMI Key
16 0x300 2048 bit Security boot key
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| /linux-6.12.1/drivers/media/platform/mediatek/mdp3/ |
| D | mdp_reg_rsz.h | 10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
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| D | mdp_reg_wdma.h | 10 #define WDMA_EN 0x008
11 #define WDMA_RST 0x00c
12 #define WDMA_CFG 0x014
13 #define WDMA_SRC_SIZE 0x018
14 #define WDMA_CLIP_SIZE 0x01c
15 #define WDMA_CLIP_COORD 0x020
16 #define WDMA_DST_W_IN_BYTE 0x028
17 #define WDMA_ALPHA 0x02c
18 #define WDMA_BUF_CON2 0x03c
19 #define WDMA_DST_UV_PITCH 0x078
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
| D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
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| /linux-6.12.1/drivers/bus/ |
| D | omap_l3_smx.h | 14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
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| /linux-6.12.1/include/linux/amba/ |
| D | sp810.h | 18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
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| /linux-6.12.1/drivers/clk/meson/ |
| D | axg-audio.h | 16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_SW_RESET 0x024
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
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| /linux-6.12.1/sound/soc/meson/ |
| D | aiu.h | 18 PCLK = 0,
62 #define AIU_IEC958_BPF 0x000
63 #define AIU_958_MISC 0x010
64 #define AIU_IEC958_DCU_FF_CTRL 0x01c
65 #define AIU_958_CHSTAT_L0 0x020
66 #define AIU_958_CHSTAT_L1 0x024
67 #define AIU_958_CTRL 0x028
68 #define AIU_I2S_SOURCE_DESC 0x034
69 #define AIU_I2S_DAC_CFG 0x040
70 #define AIU_I2S_SYNC 0x044
[all …]
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