Lines Matching +full:0 +full:x028

10 #define QSERDES_DP_PHY_REVISION_ID0			0x000
11 #define QSERDES_DP_PHY_REVISION_ID1			0x004
12 #define QSERDES_DP_PHY_REVISION_ID2			0x008
13 #define QSERDES_DP_PHY_REVISION_ID3			0x00c
14 #define QSERDES_DP_PHY_CFG				0x010
15 #define QSERDES_DP_PHY_CFG_1				0x014
16 #define QSERDES_DP_PHY_PD_CTL				0x018
17 #define QSERDES_DP_PHY_MODE				0x01c
18 #define QSERDES_DP_PHY_AUX_CFG0				0x020
19 #define QSERDES_DP_PHY_AUX_CFG1				0x024
20 #define QSERDES_DP_PHY_AUX_CFG2				0x028
21 #define QSERDES_DP_PHY_AUX_CFG3				0x02c
22 #define QSERDES_DP_PHY_AUX_CFG4				0x030
23 #define QSERDES_DP_PHY_AUX_CFG5				0x034
24 #define QSERDES_DP_PHY_AUX_CFG6				0x038
25 #define QSERDES_DP_PHY_AUX_CFG7				0x03c
26 #define QSERDES_DP_PHY_AUX_CFG8				0x040
27 #define QSERDES_DP_PHY_AUX_CFG9				0x044
30 # define QSERDES_V3_COM_BIAS_EN				0x0001
31 # define QSERDES_V3_COM_BIAS_EN_MUX			0x0002
32 # define QSERDES_V3_COM_CLKBUF_R_EN			0x0004
33 # define QSERDES_V3_COM_CLKBUF_L_EN			0x0008
34 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010
35 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020
36 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040
39 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f
40 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020
43 # define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f
44 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020
47 # define DP_PHY_PD_CTL_PWRDN				0x001
48 # define DP_PHY_PD_CTL_PSR_PWRDN			0x002
49 # define DP_PHY_PD_CTL_AUX_PWRDN			0x004
50 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN			0x008
51 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN			0x010
52 # define DP_PHY_PD_CTL_PLL_PWRDN			0x020
53 # define DP_PHY_PD_CTL_DP_CLAMP_EN			0x040
56 # define PHY_AUX_STOP_ERR_MASK				0x01
57 # define PHY_AUX_DEC_ERR_MASK				0x02
58 # define PHY_AUX_SYNC_ERR_MASK				0x04
59 # define PHY_AUX_ALIGN_ERR_MASK				0x08
60 # define PHY_AUX_REQ_ERR_MASK				0x10