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/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtc8822bwifionly.c9 halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
11 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
13 halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
15 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
17 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
19 halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
20 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
21 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
22 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
41 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-qcs404.yaml27 - description: PCIe 0 PIPE clock (optional)
28 - description: DSI phy instance 0 dsi clock
29 - description: DSI phy instance 0 byte clock
54 reg = <0x01800000 0x80000>;
Dqcom,ipq5332-gcc.yaml47 reg = <0x01800000 0x80000>;
Dqcom,gcc-ipq6018.yaml52 reg = <0x01800000 0x80000>;
Dqcom,gcc-ipq8074.yaml50 reg = <0x01800000 0x80000>;
Dqcom,gcc-msm8909.yaml31 - description: DSI phy instance 0 dsi clock
32 - description: DSI phy instance 0 byte clock
56 reg = <0x01800000 0x80000>;
60 clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>;
Dqcom,ipq9574-gcc.yaml54 reg = <0x01800000 0x80000>;
Dqcom,ipq5018-gcc.yaml51 reg = <0x01800000 0x80000>;
Dqcom,gcc-msm8953.yaml58 reg = <0x01800000 0x80000>;
62 <&dsi0_phy 0>,
64 <&dsi1_phy 0>;
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-am642-tqma64xxl.dtsi19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
36 reg = <0x00 0xa0000000 0x00 0x100000>;
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
48 reg = <0x00 0xa1000000 0x00 0x100000>;
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
60 reg = <0x00 0xa2000000 0x00 0x100000>;
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
72 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/sn0/
Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dtraps.h29 #define VEC_RESETSP (0)
100 #define PS_T (0x8000)
101 #define PS_S (0x2000)
102 #define PS_M (0x1000)
103 #define PS_C (0x0001)
107 #define FC (0x8000)
108 #define FB (0x4000)
109 #define RC (0x2000)
110 #define RB (0x1000)
111 #define DF (0x0100)
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dgamecube.dts24 reg = <0x00000000 0x01800000>;
29 #size-cells = <0>;
31 PowerPC,gekko@0 {
33 reg = <0>;
49 ranges = <0x0c000000 0x0c000000 0x00010000>;
54 reg = <0x0c002000 0x100>;
60 reg = <0x0c003000 0x100>;
73 reg = <0x0c005000 0x200>;
76 memory@0 {
78 reg = <0 0x1000000>; /* 16MB */
[all …]
Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/linux-6.12.1/arch/sh/include/mach-common/mach/
Dsdk7780.h16 #define PA_ROM 0xa0000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0xa0800000 /* Flash-ROM */
19 #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
20 #define PA_EXT1 0xa4000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
23 #define PA_SDRAM_SIZE 0x08000000
25 #define PA_EXT4 0xb0000000
26 #define PA_EXT4_SIZE 0x04000000
[all …]
/linux-6.12.1/arch/sh/include/mach-se/mach/
Dse7722.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
23 #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE 0x04000000
26 #define PA_EXT4 0xb0000000
27 #define PA_EXT4_SIZE 0x04000000
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgpucc-sc8280xp.c41 { 249600000, 1800000000, 0 },
45 .l = 0x1c,
46 .alpha = 0xa555,
47 .config_ctl_val = 0x20485699,
48 .config_ctl_hi_val = 0x00002261,
49 .config_ctl_hi1_val = 0x2a9a699c,
50 .test_ctl_val = 0x00000000,
51 .test_ctl_hi_val = 0x00000000,
52 .test_ctl_hi1_val = 0x01800000,
53 .user_ctl_val = 0x00000000,
[all …]
Dvideocc-sm8350.c41 { 249600000, 1750000000, 0 },
45 { 249600000, 1800000000, 0 },
49 .l = 0x25,
50 .alpha = 0x8000,
51 .config_ctl_val = 0x20485699,
52 .config_ctl_hi_val = 0x00002261,
53 .config_ctl_hi1_val = 0x2a9a699c,
54 .test_ctl_val = 0x00000000,
55 .test_ctl_hi_val = 0x00000000,
56 .test_ctl_hi1_val = 0x01800000,
[all …]
Dgpucc-sm8350.c38 { 249600000, 1750000000, 0 },
42 .l = 0x18,
43 .alpha = 0x6000,
44 .config_ctl_val = 0x20485699,
45 .config_ctl_hi_val = 0x00002261,
46 .config_ctl_hi1_val = 0x2a9a699c,
47 .test_ctl_val = 0x00000000,
48 .test_ctl_hi_val = 0x00000000,
49 .test_ctl_hi1_val = 0x01800000,
50 .user_ctl_val = 0x00000000,
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-rc32434/
Dddr.h49 #define DDR0_PHYS_ADDR 0x18018000
52 #define DDR_MASK 0xffff0000
58 #define RC32434_DDR0_ATA_MSK 0x000000E0
60 #define RC32434_DDR0_DBW_MSK 0x00000100
62 #define RC32434_DDR0_WR_MSK 0x00000600
64 #define RC32434_DDR0_PS_MSK 0x00001800
66 #define RC32434_DDR0_DTYPE_MSK 0x0000e000
68 #define RC32434_DDR0_RFC_MSK 0x000f0000
70 #define RC32434_DDR0_RP_MSK 0x00300000
72 #define RC32434_DDR0_AP_MSK 0x00400000
[all …]
/linux-6.12.1/arch/mips/include/asm/ip32/
Dcrime.h18 #define CRIME_BASE 0x14000000 /* physical */
22 #define CRIME_ID_MASK 0xff
23 #define CRIME_ID_IDBITS 0xf0
24 #define CRIME_ID_IDVALUE 0xa0
25 #define CRIME_ID_REV 0x0f
26 #define CRIME_REV_PETTY 0x00
27 #define CRIME_REV_11 0x11
28 #define CRIME_REV_13 0x13
29 #define CRIME_REV_14 0x14
32 #define CRIME_CONTROL_MASK 0x3fff
[all …]
/linux-6.12.1/sound/soc/amd/
Dacp.h8 #define ACP_PAGE_SIZE_4K_ENABLE 0x02
11 #define ACP_CAPTURE_PTE_OFFSET 0
14 #define ACP_ST_PLAYBACK_PTE_OFFSET 0x04
15 #define ACP_ST_CAPTURE_PTE_OFFSET 0x00
16 #define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08
17 #define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c
19 #define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4
20 #define ACP_ONION_CNTL_DEFAULT 0x00000FB4
22 #define ACP_PHYSICAL_BASE 0x14000
32 #define ACP_SRAM_BANK_1_ADDRESS 0x4002000
[all …]
/linux-6.12.1/sound/soc/sof/amd/
Dacp-stream.c18 #define PTE_GRP1_OFFSET 0x00000000
19 #define PTE_GRP2_OFFSET 0x00800000
20 #define PTE_GRP3_OFFSET 0x01000000
21 #define PTE_GRP4_OFFSET 0x01800000
22 #define PTE_GRP5_OFFSET 0x02000000
23 #define PTE_GRP6_OFFSET 0x02800000
24 #define PTE_GRP7_OFFSET 0x03000000
25 #define PTE_GRP8_OFFSET 0x03800000
106 for (page_idx = 0; page_idx < stream->num_pages; page_idx++) { in acp_dsp_stream_config()
124 return 0; in acp_dsp_stream_config()
[all …]
/linux-6.12.1/sound/soc/sh/rcar/
Dsrc.c51 for ((i) = 0; \
69 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_activation()
76 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_halt()
98 return 0; in rsnd_src_convert_rate()
120 unsigned int rate = 0; in rsnd_src_get_rate()
148 0x01800000, /* 6 - 1/6 */
149 0x01000000, /* 6 - 1/4 */
150 0x00c00000, /* 6 - 1/3 */
151 0x00800000, /* 6 - 1/2 */
152 0x00600000, /* 6 - 2/3 */
[all …]

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