clk/qcom/gpucc-sc8280xp.c

41 	{ 249600000, 1800000000, 0 },
45 	.l = 0x1c,
46 	.alpha = 0xa555,
47 	.config_ctl_val = 0x20485699,
48 	.config_ctl_hi_val = 0x00002261,
49 	.config_ctl_hi1_val = 0x2a9a699c,
50 	.test_ctl_val = 0x00000000,
51 	.test_ctl_hi_val = 0x00000000,
52 	.test_ctl_hi1_val = 0x01800000,
53 	.user_ctl_val = 0x00000000,
54 	.user_ctl_hi_val = 0x00000805,
55 	.user_ctl_hi1_val = 0x00000000,
59 	.offset = 0x0,
74 	.l = 0x1A,
75 	.alpha = 0xaaa,
76 	.config_ctl_val = 0x20485699,
77 	.config_ctl_hi_val = 0x00002261,
78 	.config_ctl_hi1_val = 0x2a9a699c,
79 	.test_ctl_val = 0x00000000,
80 	.test_ctl_hi_val = 0x00000000,
81 	.test_ctl_hi1_val = 0x01800000,
82 	.user_ctl_val = 0x00000000,
83 	.user_ctl_hi_val = 0x00000805,
84 	.user_ctl_hi1_val = 0x00000000,
88 	.offset = 0x100,
103 	{ P_BI_TCXO, 0 },
119 	{ P_BI_TCXO, 0 },
133 	F(19200000, P_BI_TCXO, 1, 0, 0),
134 	F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
135 	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
140 	.cmd_rcgr = 0x1120,
141 	.mnd_width = 0,
154 	F(200000000, P_GCC_GPU_GPLL0_CLK_SRC, 3, 0, 0),
155 	F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0),
156 	F(400000000, P_GCC_GPU_GPLL0_CLK_SRC, 1.5, 0, 0),
161 	.cmd_rcgr = 0x117c,
162 	.mnd_width = 0,
175 	.reg = 0x11c0,
176 	.shift = 0,
190 	.reg = 0x11bc,
191 	.shift = 0,
205 	.halt_reg = 0x1078,
208 		.enable_reg = 0x1078,
209 		.enable_mask = BIT(0),
223 	.halt_reg = 0x107c,
226 		.enable_reg = 0x107c,
227 		.enable_mask = BIT(0),
241 	.halt_reg = 0x1098,
244 		.enable_reg = 0x1098,
245 		.enable_mask = BIT(0),
259 	.halt_reg = 0x108c,
262 		.enable_reg = 0x108c,
263 		.enable_mask = BIT(0),
272 	.halt_reg = 0x1004,
275 		.enable_reg = 0x1004,
276 		.enable_mask = BIT(0),
285 	.halt_reg = 0x1064,
288 		.enable_reg = 0x1064,
289 		.enable_mask = BIT(0),
303 	.halt_reg = 0x5000,
306 		.enable_reg = 0x5000,
307 		.enable_mask = BIT(0),
316 	.halt_reg = 0x1178,
319 		.enable_reg = 0x1178,
320 		.enable_mask = BIT(0),
334 	.halt_reg = 0x1204,
337 		.enable_reg = 0x1204,
338 		.enable_mask = BIT(0),
352 	.halt_reg = 0x1090,
355 		.enable_reg = 0x1090,
356 		.enable_mask = BIT(0),
384 	.gdscr = 0x106c,
385 	.gds_hw_ctrl = 0x1540,
394 	.gdscr = 0x100c,
395 	.clamp_io_ctrl = 0x1508,
414 	.max_register = 0x8030,
449 	qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */  in gpu_cc_sc8280xp_probe()
450 	qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */  in gpu_cc_sc8280xp_probe()