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/linux-6.12.1/arch/arm/boot/dts/nxp/mxs/
Dimx28-m28cu3.dts15 reg = <0x40000000 0x08000000>;
20 pwms = <&pwm 3 5000000 0>;
21 brightness-levels = <0 4 8 16 32 64 128 255>;
28 pinctrl-0 = <&led_pins_gpio>;
32 gpios = <&gpio2 26 0>;
38 gpios = <&gpio2 24 0>;
43 reg_3p3v: regulator-0 {
56 gpio = <&gpio3 29 0>;
64 gpio = <&gpio2 19 0>;
72 gpio = <&gpio3 8 0>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sm6115.yaml48 reg = <0x01400000 0x1f0000>;
Dqcom,gcc-sm6125.yaml48 reg = <0x01400000 0x1f0000>;
Dqcom,sm6375-gcc.yaml43 reg = <0x01400000 0x1f0000>;
Dqcom,gcc-qcm2290.yaml48 reg = <0x01400000 0x1f0000>;
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dallwinner,sun8i-h3-deinterlace.yaml72 reg = <0x01400000 0x20000>;
/linux-6.12.1/arch/powerpc/boot/
Dof.c17 #define PROG_START 0x01400000 /* only used on 64-bit systems */
19 #define ONE_MB 0x100000
30 unsigned long addr = 0; in of_try_claim()
32 if (claim_base == 0) in of_try_claim()
37 printf(" trying: 0x%08lx\n\r", claim_base); in of_try_claim()
39 addr = (unsigned long) of_claim(claim_base, size, 0); in of_try_claim()
43 if (addr == 0) in of_try_claim()
78 if (a1 && a2 && a2 != 0xdeadbeef) { in of_platform_init()
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dp1010rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x2000000>;
46 reg = <0x00040000 0x00040000>;
52 reg = <0x00080000 0x00700000>;
58 reg = <0x00800000 0x01400000>;
66 reg = <0x01f00000 0x00100000>;
72 ifc_nand: nand@1,0 {
76 reg = <0x1 0x0 0x10000>;
79 cpld@3,0 {
83 reg = <0x3 0x0 0x0000020>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/allwinner/
Dsun8i-h3.dtsi72 #size-cells = <0>;
74 cpu0: cpu@0 {
77 reg = <0>;
155 reg = <0x01400000 0x20000>;
168 reg = <0x01c00000 0x1000>;
175 reg = <0x01d00000 0x80000>;
178 ranges = <0 0x01d00000 0x80000>;
180 ve_sram: sram-section@0 {
183 reg = <0x000000 0x80000>;
190 reg = <0x01c0e000 0x1000>;
[all …]
Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath11k/
Dcore.c28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
43 .name = "ipq8074 hw2.0",
45 .dir = "IPQ8074/hw2.0",
50 .bdf_addr = 0x4B0C0000,
76 .summary_pad_sz = 0,
93 .fw_mem_mode = 0,
129 .name = "ipq6018 hw1.0",
131 .dir = "IPQ6018/hw1.0",
136 .bdf_addr = 0x4ABC0000,
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dyosemite.dts19 dcr-parent = <&{/cpus/cpu@0}>;
32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0x00000000>;
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
Deiger.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
[all …]
Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
Dglacier.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
/linux-6.12.1/include/video/
Dnewport.h34 #define DM1_PLANES 0x00000007
35 #define DM1_NOPLANES 0x00000000
36 #define DM1_RGBPLANES 0x00000001
37 #define DM1_RGBAPLANES 0x00000002
38 #define DM1_OLAYPLANES 0x00000004
39 #define DM1_PUPPLANES 0x00000005
40 #define DM1_CIDPLANES 0x00000006
42 #define NPORT_DMODE1_DDMASK 0x00000018
43 #define NPORT_DMODE1_DD4 0x00000000
44 #define NPORT_DMODE1_DD8 0x00000008
[all …]
/linux-6.12.1/include/soc/fsl/qe/
Dqe.h34 QE_CLK_NONE = 0,
150 return 0; in cpm_muram_dma()
245 return 0; in qe_alive_during_sleep()
291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
304 __be32 traps[16]; /* Trap addresses, 0 == ignore */
348 #define BD_STATUS_MASK 0xffff0000
349 #define BD_LENGTH_MASK 0x0000ffff
357 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
358 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
359 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/linux-6.12.1/sound/firewire/fireface/
Dff-protocol-former.c10 #define FORMER_REG_SYNC_STATUS 0x0000801c0000ull
12 #define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
13 #define FORMER_REG_CLOCK_CONFIG 0x0000801c0004ull
22 { 32000, 0x00000002, }, in parse_clock_bits()
23 { 44100, 0x00000000, }, in parse_clock_bits()
24 { 48000, 0x00000006, }, in parse_clock_bits()
25 { 64000, 0x0000000a, }, in parse_clock_bits()
26 { 88200, 0x00000008, }, in parse_clock_bits()
27 { 96000, 0x0000000e, }, in parse_clock_bits()
28 { 128000, 0x00000012, }, in parse_clock_bits()
[all …]
/linux-6.12.1/arch/hexagon/kernel/
Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Ds626.h36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
39 #define S626_EOPL 0x80 /* End of ADC poll list marker. */
40 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */
44 #define S626_ERR_ILLEGAL_PARM 0x00010000 /*
48 #define S626_ERR_I2C 0x00020000 /* I2C error. */
49 #define S626_ERR_COUNTERSETUP 0x00200000 /*
53 #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
74 #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsm6125.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]
Dqcm2290.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
49 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
67 reg = <0x0 0x1>;
68 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6375.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]

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