Lines Matching +full:0 +full:x01400000
10 #define FORMER_REG_SYNC_STATUS 0x0000801c0000ull
12 #define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
13 #define FORMER_REG_CLOCK_CONFIG 0x0000801c0004ull
22 { 32000, 0x00000002, }, in parse_clock_bits()
23 { 44100, 0x00000000, }, in parse_clock_bits()
24 { 48000, 0x00000006, }, in parse_clock_bits()
25 { 64000, 0x0000000a, }, in parse_clock_bits()
26 { 88200, 0x00000008, }, in parse_clock_bits()
27 { 96000, 0x0000000e, }, in parse_clock_bits()
28 { 128000, 0x00000012, }, in parse_clock_bits()
29 { 176400, 0x00000010, }, in parse_clock_bits()
30 { 192000, 0x00000016, }, in parse_clock_bits()
36 { SND_FF_CLOCK_SRC_ADAT1, 0x00000000, }, in parse_clock_bits()
37 { SND_FF_CLOCK_SRC_ADAT2, 0x00000400, }, in parse_clock_bits()
38 { SND_FF_CLOCK_SRC_SPDIF, 0x00000c00, }, in parse_clock_bits()
39 { SND_FF_CLOCK_SRC_WORD, 0x00001000, }, in parse_clock_bits()
40 { SND_FF_CLOCK_SRC_LTC, 0x00001800, }, in parse_clock_bits()
44 for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) { in parse_clock_bits()
46 if ((data & 0x0000001e) == rate_entry->mask) { in parse_clock_bits()
54 if (data & 0x00000001) { in parse_clock_bits()
57 for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) { in parse_clock_bits()
59 if ((data & 0x00001c00) == clk_entry->mask) { in parse_clock_bits()
68 return 0; in parse_clock_bits()
79 FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0); in former_get_clock()
80 if (err < 0) in former_get_clock()
94 count = 0; in former_switch_fetching_mode()
95 for (i = 0; i < SND_FF_STREAM_MODE_COUNT; ++i) in former_switch_fetching_mode()
110 for (i = 0; i < count; ++i) in former_switch_fetching_mode()
111 reg[i] = cpu_to_le32(0x00000001); in former_switch_fetching_mode()
116 sizeof(__le32) * count, 0); in former_switch_fetching_mode()
131 FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0); in dump_clock_config()
132 if (err < 0) in dump_clock_config()
137 (data & 0x00000020) ? "Professional" : "Consumer", in dump_clock_config()
138 (data & 0x00000040) ? "on" : "off"); in dump_clock_config()
141 (data & 0x00000100) ? "S/PDIF" : "ADAT"); in dump_clock_config()
144 (data & 0x00002000) ? "on" : "off"); in dump_clock_config()
147 (data & 0x00000200) ? "Optical" : "Coaxial"); in dump_clock_config()
150 if (err < 0) in dump_clock_config()
166 { "WDClk", 0x40000000, 0x20000000, }, in dump_sync_status()
167 { "S/PDIF", 0x00080000, 0x00040000, }, in dump_sync_status()
168 { "ADAT1", 0x00000400, 0x00001000, }, in dump_sync_status()
169 { "ADAT2", 0x00000800, 0x00002000, }, in dump_sync_status()
175 { "ADAT1", 0x00000000, }, in dump_sync_status()
176 { "ADAT2", 0x00400000, }, in dump_sync_status()
177 { "S/PDIF", 0x00c00000, }, in dump_sync_status()
178 { "WDclk", 0x01000000, }, in dump_sync_status()
179 { "TCO", 0x01400000, }, in dump_sync_status()
185 { 32000, 0x02000000, }, in dump_sync_status()
186 { 44100, 0x04000000, }, in dump_sync_status()
187 { 48000, 0x06000000, }, in dump_sync_status()
188 { 64000, 0x08000000, }, in dump_sync_status()
189 { 88200, 0x0a000000, }, in dump_sync_status()
190 { 96000, 0x0c000000, }, in dump_sync_status()
191 { 128000, 0x0e000000, }, in dump_sync_status()
192 { 176400, 0x10000000, }, in dump_sync_status()
193 { 192000, 0x12000000, }, in dump_sync_status()
201 FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0); in dump_sync_status()
202 if (err < 0) in dump_sync_status()
204 data[0] = le32_to_cpu(reg[0]); in dump_sync_status()
209 for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) { in dump_sync_status()
213 if (data[0] & clk_entry->locked_mask) { in dump_sync_status()
214 if (data[0] & clk_entry->synced_mask) in dump_sync_status()
227 if (data[1] & 0x00000001) { in dump_sync_status()
233 for (i = 0; i < ARRAY_SIZE(referred_entries); ++i) { in dump_sync_status()
235 if ((data[0] & 0x1e0000) == referred_entry->mask) { in dump_sync_status()
243 for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) { in dump_sync_status()
245 if ((data[0] & 0x1e000000) == rate_entry->mask) { in dump_sync_status()
251 rate = 0; in dump_sync_status()
274 if (len <= 0) in former_fill_midi_msg()
278 for (i = len - 1; i >= 0; --i) in former_fill_midi_msg()
285 #define FF800_STF 0x0000fc88f000
286 #define FF800_RX_PACKET_FORMAT 0x0000fc88f004
287 #define FF800_ALLOC_TX_STREAM 0x0000fc88f008
288 #define FF800_ISOC_COMM_START 0x0000fc88f00c
289 #define FF800_TX_S800_FLAG 0x00000800
290 #define FF800_ISOC_COMM_STOP 0x0000fc88f010
292 #define FF800_TX_PACKET_ISOC_CH 0x0000801c0008
303 FF800_ALLOC_TX_STREAM, ®, sizeof(reg), 0); in allocate_tx_resources()
304 if (err < 0) in allocate_tx_resources()
308 count = 0; in allocate_tx_resources()
312 FF800_TX_PACKET_ISOC_CH, ®, sizeof(reg), 0); in allocate_tx_resources()
313 if (err < 0) in allocate_tx_resources()
317 if (data != 0xffffffff) { in allocate_tx_resources()
332 return 0; in allocate_tx_resources()
343 FF800_STF, ®, sizeof(reg), 0); in ff800_allocate_resources()
344 if (err < 0) in ff800_allocate_resources()
356 if (err < 0) in ff800_allocate_resources()
366 FF800_RX_PACKET_FORMAT, ®, sizeof(reg), 0); in ff800_allocate_resources()
367 if (err < 0) in ff800_allocate_resources()
380 if (err < 0) in ff800_begin_session()
384 reg = cpu_to_le32(0x80000000); in ff800_begin_session()
389 FF800_ISOC_COMM_START, ®, sizeof(reg), 0); in ff800_begin_session()
396 reg = cpu_to_le32(0x80000000); in ff800_finish_session()
398 FF800_ISOC_COMM_STOP, ®, sizeof(reg), 0); in ff800_finish_session()
410 for (i = 0; i < length / 4; i++) { in ff800_handle_midi_msg()
411 u8 byte = le32_to_cpu(buf[i]) & 0xff; in ff800_handle_midi_msg()
414 substream = READ_ONCE(ff->tx_midi_substreams[0]); in ff800_handle_midi_msg()
431 #define FF400_STF 0x000080100500ull
432 #define FF400_RX_PACKET_FORMAT 0x000080100504ull
433 #define FF400_ISOC_COMM_START 0x000080100508ull
434 #define FF400_TX_PACKET_FORMAT 0x00008010050cull
435 #define FF400_ISOC_COMM_STOP 0x000080100510ull
438 // we can allocate between 0 and 7 channel.
447 for (i = 0; i < CIP_SFC_COUNT; i++) { in ff400_allocate_resources()
457 FF400_STF, ®, sizeof(reg), 0); in ff400_allocate_resources()
458 if (err < 0) in ff400_allocate_resources()
464 if (err < 0) in ff400_allocate_resources()
468 ff->tx_resources.channels_mask = 0x00000000000000ffuLL; in ff400_allocate_resources()
472 if (err < 0) in ff400_allocate_resources()
476 ff->rx_resources.channels_mask = 0x00000000000000ffuLL; in ff400_allocate_resources()
480 if (err < 0) in ff400_allocate_resources()
494 if (err < 0) in ff400_begin_session()
498 if (err < 0) in ff400_begin_session()
507 FF400_RX_PACKET_FORMAT, ®, sizeof(reg), 0); in ff400_begin_session()
508 if (err < 0) in ff400_begin_session()
513 // TODO: investigate the purpose of this 0x80. in ff400_begin_session()
514 reg = cpu_to_le32((0x80 << 24) | in ff400_begin_session()
518 FF400_TX_PACKET_FORMAT, ®, sizeof(reg), 0); in ff400_begin_session()
519 if (err < 0) in ff400_begin_session()
523 reg = cpu_to_le32(0x00000001); in ff400_begin_session()
525 FF400_ISOC_COMM_START, ®, sizeof(reg), 0); in ff400_begin_session()
532 reg = cpu_to_le32(0x80000000); in ff400_finish_session()
534 FF400_ISOC_COMM_STOP, ®, sizeof(reg), 0); in ff400_finish_session()
542 u8 byte = (quad >> (16 * port)) & 0x000000ff; in parse_midi_msg()
567 // flag in quadlet register (little endian) at 0x'0000'801'0051c. Drivers can
571 // - 0x04000000: 0x'....'....'0000'0000
572 // - 0x08000000: 0x'....'....'0000'0080
573 // - 0x10000000: 0x'....'....'0000'0100
574 // - 0x20000000: 0x'....'....'0000'0180
578 // - 0x01000000: suppress transmission
579 // - 0x02000000: suppress transmission
588 // - 0: Microphone input 0/1
589 // - 1: Line input 0/1
590 // - [2-4]: Line output 0-5
591 // - 5: Headphone output 0/1
592 // - 6: S/PDIF output 0/1
593 // - [7-10]: ADAT output 0-7
595 // The value of signal level can be detected by mask of 0x00fffc00. For signal level of microphone
598 // - 0: 0.0 dB
609 // - 0: 0.0 dB
633 // - 0: +6.0 dB
636 // FF400_MSG_FLAG_IS_MIDI_PORT_0, one MIDI byte can be detected by mask of 0x000000ff. When
637 // matching to FF400_MSG_FLAG_IS_MIDI_PORT_1, one MIDI byte can be detected by mask of 0x00ff0000.
638 #define FF400_MSG_FLAG_IS_SIGNAL_LEVEL 0x04000000
639 #define FF400_MSG_FLAG_IS_RIGHT_CHANNEL 0x08000000
640 #define FF400_MSG_FLAG_IS_STEREO_PAIRED 0x02000000
641 #define FF400_MSG_MASK_STEREO_PAIR 0xf0000000
642 #define FF400_MSG_MASK_SIGNAL_LEVEL 0x00fffc00
643 #define FF400_MSG_FLAG_IS_MIDI_PORT_0 0x00000100
644 #define FF400_MSG_MASK_MIDI_PORT_0 0x000000ff
645 #define FF400_MSG_FLAG_IS_MIDI_PORT_1 0x01000000
646 #define FF400_MSG_MASK_MIDI_PORT_1 0x00ff0000
654 for (i = 0; i < length / 4; i++) { in ff400_handle_msg()
664 parser->push_pos = 0; in ff400_handle_msg()
668 parse_midi_msg(ff, quad, 0); in ff400_handle_msg()
682 .message_count = 0, in ff400_copy_msg_to_user()
685 long consumed = 0; in ff400_copy_msg_to_user()
686 long ret = 0; in ff400_copy_msg_to_user()
689 return 0; in ff400_copy_msg_to_user()
705 parser->pull_pos = 0; in ff400_copy_msg_to_user()