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/linux-6.12.1/Documentation/devicetree/bindings/dma/
Darm-pl08x.yaml109 reg = <0x10130000 0x1000>;
128 arm,primecell-periphid = <0x0003b080>;
129 reg = <0x67000000 0x1000>;
/linux-6.12.1/arch/arm/boot/dts/gemini/
Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
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/linux-6.12.1/drivers/dma/
Damba-pl08x.c207 * trigger this txd. Other registers are in llis_va[0].
298 #define PL080_LLI_SRC 0
338 if (plchan->mux_use++ == 0 && pd->get_xfer_signal) { in pl08x_request_mux()
340 if (ret < 0) { in pl08x_request_mux()
341 plchan->mux_use = 0; in pl08x_request_mux()
347 return 0; in pl08x_request_mux()
354 if (plchan->signal >= 0) { in pl08x_release_mux()
355 WARN_ON(plchan->mux_use == 0); in pl08x_release_mux()
357 if (--plchan->mux_use == 0 && pd->put_xfer_signal) { in pl08x_release_mux()
396 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " in pl08x_write_lli()
[all …]