207 	 * trigger this txd.  Other registers are in llis_va[0].
298 #define PL080_LLI_SRC		0
338 	if (plchan->mux_use++ == 0 && pd->get_xfer_signal) {  in pl08x_request_mux()
340 		if (ret < 0) {  in pl08x_request_mux()
341 			plchan->mux_use = 0;  in pl08x_request_mux()
347 	return 0;  in pl08x_request_mux()
354 	if (plchan->signal >= 0) {  in pl08x_release_mux()
355 		WARN_ON(plchan->mux_use == 0);  in pl08x_release_mux()
357 		if (--plchan->mux_use == 0 && pd->put_xfer_signal) {  in pl08x_release_mux()
396 			"WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "  in pl08x_write_lli()
397 			"clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n",  in pl08x_write_lli()
403 			"WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "  in pl08x_write_lli()
404 			"clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",  in pl08x_write_lli()
420 		u32 val = 0;  in pl08x_write_lli()
543 	pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg);  in pl08x_start_next_txd()
768 		return 0;  in pl08x_getbytes_chan()
825 	for (i = 0; i < pl08x->vd->channels; i++) {  in pl08x_get_phy_channel()
1000 	return 0;  in pl08x_get_bytes_for_lli()
1224 		for (i = 0; i < num_llis; i++) {  in pl08x_dump_lli()
1226 				"%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",  in pl08x_dump_lli()
1237 		for (i = 0; i < num_llis; i++) {  in pl08x_dump_lli()
1239 				"%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",  in pl08x_dump_lli()
1255  * Return 0 for error
1262 	int num_llis = 0;  in pl08x_fill_llis_for_desc()
1263 	u32 cctl, early_bytes = 0;  in pl08x_fill_llis_for_desc()
1271 		return 0;  in pl08x_fill_llis_for_desc()
1275 	bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;  in pl08x_fill_llis_for_desc()
1285 		total_bytes = 0;  in pl08x_fill_llis_for_desc()
1297 			"src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",  in pl08x_fill_llis_for_desc()
1343 				return 0;  in pl08x_fill_llis_for_desc()
1352 				return 0;  in pl08x_fill_llis_for_desc()
1357 					0);  in pl08x_fill_llis_for_desc()
1359 					0, cctl, 0);  in pl08x_fill_llis_for_desc()
1379 				"%s byte width LLIs (remain 0x%08zx)\n",  in pl08x_fill_llis_for_desc()
1433 					"size 0x%08zx (remainder 0x%08zx)\n",  in pl08x_fill_llis_for_desc()
1458 				"%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",  in pl08x_fill_llis_for_desc()
1460 			return 0;  in pl08x_fill_llis_for_desc()
1465 				"%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",  in pl08x_fill_llis_for_desc()
1467 			return 0;  in pl08x_fill_llis_for_desc()
1479 		last_lli[PL080_LLI_LLI] = 0;  in pl08x_fill_llis_for_desc()
1550 	size_t bytes = 0;  in pl08x_dma_tx_status()
1632 		.burstwords = 0,
1644 	u32 cctl = 0;  in pl08x_select_bus()
1685 		return ~0;  in pl08x_width()
1693 	for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)  in pl08x_burst()
1703 	u32 width, burst, cctl = 0;  in pl08x_get_cctl()
1706 	if (width == ~0)  in pl08x_get_cctl()
1707 		return ~0;  in pl08x_get_cctl()
1755 	u32 cctl = 0;  in pl08x_memcpy_cctl()
1838 	u32 cctl = 0;  in pl08x_ftdmac020_memcpy_cctl()
1910 		txd->ccfg = 0;  in pl08x_prep_dma_memcpy()
1974 	if (cctl == ~0) {  in pl08x_init_txd()
1995 	if (ret < 0) {  in pl08x_init_txd()
2038 	return 0;  in pl08x_tx_add_sg()
2106 	for (tmp = 0; tmp < buf_len; tmp += period_len) {  in pl08x_prep_dma_cyclic()
2149 	return 0;  in pl08x_config()
2161 		return 0;  in pl08x_terminate_all()
2183 	return 0;  in pl08x_terminate_all()
2205 		return 0;  in pl08x_pause()
2213 	return 0;  in pl08x_pause()
2228 		return 0;  in pl08x_resume()
2236 	return 0;  in pl08x_resume()
2287 	u32 mask = 0, err, tc, i;  in pl08x_irq()
2292 		dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",  in pl08x_irq()
2303 	for (i = 0; i < pl08x->vd->channels; i++) {  in pl08x_irq()
2312 					"%s Error TC interrupt on unused channel: 0x%08x\n",  in pl08x_irq()
2374 	for (i = 0; i < channels; i++) {  in pl08x_dma_init_virtual_channels()
2460 	for (i = 0; i < pl08x->vd->channels; i++) {  in pl08x_debugfs_show()
2495 	return 0;  in pl08x_debugfs_show()
2547 	dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]);  in pl08x_of_xlate()
2557 		dma_spec->args[0]);  in pl08x_of_xlate()
2669 		for (i = 0; i < pl08x->vd->signals; i++) {  in pl08x_of_probe()
2699 	int ret = 0;  in pl08x_probe()
2733 			 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);  in pl08x_probe()
2737 			 (val >> 12) & 0x0f,  in pl08x_probe()
2746 		vd->channels = (val >> 12) & 0x0f;  in pl08x_probe()
2832 						tsfr_size, PL08X_ALIGN, 0);  in pl08x_probe()
2844 		writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);  in pl08x_probe()
2846 		writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);  in pl08x_probe()
2847 	writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);  in pl08x_probe()
2850 	ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x);  in pl08x_probe()
2853 			__func__, adev->irq[0]);  in pl08x_probe()
2865 	for (i = 0; i < vd->channels; i++) {  in pl08x_probe()
2913 	if (ret <= 0) {  in pl08x_probe()
2924 		if (ret < 0) {  in pl08x_probe()
2952 	dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n",  in pl08x_probe()
2954 		 (unsigned long long)adev->res.start, adev->irq[0]);  in pl08x_probe()
2956 	return 0;  in pl08x_probe()
2968 	free_irq(adev->irq[0], pl08x);  in pl08x_probe()
3024 		.id	= 0x0a141080,
3025 		.mask	= 0xffffffff,
3030 		.id	= 0x00041080,
3031 		.mask	= 0x000fffff,
3036 		.id	= 0x00041081,
3037 		.mask	= 0x000fffff,
3042 		.id	= 0x00280080,
3043 		.mask	= 0x00ffffff,
3048 		.id	= 0x0003b080,
3049 		.mask	= 0x000fffff,
3052 	{ 0, 0 },