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/linux-6.12.1/drivers/soc/qcom/
Dqcom_gsbi.c17 #define GSBI_CTRL_REG 0x0000
21 #define TCSR_ADM_CRCI_BASE 0x70
30 0x000003, 0x00000c, 0x000030, 0x0000c0,
31 0x000300, 0x000c00, 0x003000, 0x00c000,
32 0x030000, 0x0c0000, 0x300000, 0xc00000
35 0x000003, 0x00000c, 0x000030, 0x0000c0,
36 0x000300, 0x000c00, 0x003000, 0x00c000,
37 0x030000, 0x0c0000, 0x300000, 0xc00000
48 0x001800, 0x006000, 0x000030, 0x0000c0,
49 0x000300, 0x000400, 0x000000, 0x000000,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dfsl,enetc-mdio.yaml47 mdio@0,3 {
49 reg = <0x000300 0 0 0 0>;
51 #size-cells = <0>;
54 reg = <0x2>;
/linux-6.12.1/drivers/scsi/aic94xx/
Daic94xx_sds.h17 #define FLASH_MANUF_ID_AMD 0x01
18 #define FLASH_MANUF_ID_ST 0x20
19 #define FLASH_MANUF_ID_FUJITSU 0x04
20 #define FLASH_MANUF_ID_MACRONIX 0xC2
21 #define FLASH_MANUF_ID_INTEL 0x89
22 #define FLASH_MANUF_ID_UNKNOWN 0xFF
24 #define FLASH_DEV_ID_AM29LV008BT 0x3E
25 #define FLASH_DEV_ID_AM29LV800DT 0xDA
26 #define FLASH_DEV_ID_STM29W800DT 0xD7
27 #define FLASH_DEV_ID_STM29LV640 0xDE
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgk104.c37 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_vsi()
42 nvkm_mask(device, 0x690100 + hoff, 0x00010001, 0x00000000); in gk104_sor_hdmi_infoframe_vsi()
46 nvkm_wr32(device, 0x690108 + hoff, vsi.header); in gk104_sor_hdmi_infoframe_vsi()
47 nvkm_wr32(device, 0x69010c + hoff, vsi.subpack0_low); in gk104_sor_hdmi_infoframe_vsi()
48 nvkm_wr32(device, 0x690110 + hoff, vsi.subpack0_high); in gk104_sor_hdmi_infoframe_vsi()
50 nvkm_mask(device, 0x690100 + hoff, 0x00000001, 0x00000001); in gk104_sor_hdmi_infoframe_vsi()
58 const u32 hoff = head * 0x400; in gk104_sor_hdmi_infoframe_avi()
63 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000000); in gk104_sor_hdmi_infoframe_avi()
67 nvkm_wr32(device, 0x690008 + hoff, avi.header); in gk104_sor_hdmi_infoframe_avi()
68 nvkm_wr32(device, 0x69000c + hoff, avi.subpack0_low); in gk104_sor_hdmi_infoframe_avi()
[all …]
Dgf119.c40 const u32 hoff = 0x800 * head; in gf119_sor_hda_device_entry()
42 nvkm_mask(device, 0x616548 + hoff, 0x00000070, head << 4); in gf119_sor_hda_device_entry()
49 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_eld()
52 for (i = 0; i < size; i++) in gf119_sor_hda_eld()
53 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | data[i]); in gf119_sor_hda_eld()
54 for (; i < 0x60; i++) in gf119_sor_hda_eld()
55 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_sor_hda_eld()
56 nvkm_mask(device, 0x10ec10 + soff, 0x80000002, 0x80000002); in gf119_sor_hda_eld()
63 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_hpd()
64 u32 data = 0x80000000; in gf119_sor_hda_hpd()
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/sn0/
Dhubpi.h24 #define PI_BASE 0x000000
28 #define PI_CPU_PROTECT 0x000000 /* CPU Protection */
29 #define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */
30 #define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
31 #define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */
32 #define PI_CPU_NUM 0x000020 /* CPU Number ID */
33 #define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */
34 #define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */
35 #define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */
38 #define PI_CALIAS_SIZE_0 0
[all …]
/linux-6.12.1/arch/mips/include/asm/pci/
Dbridge.h30 #define BRIDGE_ATE_RAM_SIZE 0x00000400 /* 1kB ATE RAM */
32 #define BRIDGE_CONFIG_BASE 0x20000
33 #define BRIDGE_CONFIG1_BASE 0x28000
34 #define BRIDGE_CONFIG_END 0x30000
35 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000
37 #define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */
38 #define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */
39 #define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */
40 #define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */
48 #define ATE_V 0x01
[all …]
/linux-6.12.1/drivers/video/fbdev/
Dffb.c64 #define FFB_SFB8R_VOFF 0x00000000
65 #define FFB_SFB8G_VOFF 0x00400000
66 #define FFB_SFB8B_VOFF 0x00800000
67 #define FFB_SFB8X_VOFF 0x00c00000
68 #define FFB_SFB32_VOFF 0x01000000
69 #define FFB_SFB64_VOFF 0x02000000
70 #define FFB_FBC_REGS_VOFF 0x04000000
71 #define FFB_BM_FBC_REGS_VOFF 0x04002000
72 #define FFB_DFB8R_VOFF 0x04004000
73 #define FFB_DFB8G_VOFF 0x04404000
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Drv515d.h34 #define PCIE_INDEX 0x0030
35 #define PCIE_DATA 0x0034
36 #define MC_IND_INDEX 0x0070
38 #define MC_IND_DATA 0x0074
39 #define RBBM_SOFT_RESET 0x00F0
40 #define CONFIG_MEMSIZE 0x00F8
41 #define HDP_FB_LOCATION 0x0134
42 #define CP_CSQ_CNTL 0x0740
43 #define CP_CSQ_MODE 0x0744
44 #define CP_CSQ_ADDR 0x07F0
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgf108.c34 { 0x001000, 1, 0x01, 0x00000004 },
35 { 0x0000a9, 1, 0x01, 0x0000ffff },
36 { 0x000038, 1, 0x01, 0x0fac6881 },
37 { 0x00003d, 1, 0x01, 0x00000001 },
38 { 0x0000e8, 8, 0x01, 0x00000400 },
39 { 0x000078, 8, 0x01, 0x00000300 },
40 { 0x000050, 1, 0x01, 0x00000011 },
41 { 0x000058, 8, 0x01, 0x00000008 },
42 { 0x000208, 8, 0x01, 0x00000001 },
43 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
Dctxgk110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x000039, 3, 0x01, 0x00000000 },
34 { 0x0000a9, 1, 0x01, 0x0000ffff },
35 { 0x000038, 1, 0x01, 0x0fac6881 },
36 { 0x00003d, 1, 0x01, 0x00000001 },
37 { 0x0000e8, 8, 0x01, 0x00000400 },
38 { 0x000078, 8, 0x01, 0x00000300 },
39 { 0x000050, 1, 0x01, 0x00000011 },
40 { 0x000058, 8, 0x01, 0x00000008 },
41 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
Dctxgm107.c35 { 0x001000, 1, 0x01, 0x00000004 },
36 { 0x000039, 3, 0x01, 0x00000000 },
37 { 0x0000a9, 1, 0x01, 0x0000ffff },
38 { 0x000038, 1, 0x01, 0x0fac6881 },
39 { 0x00003d, 1, 0x01, 0x00000001 },
40 { 0x0000e8, 8, 0x01, 0x00000400 },
41 { 0x000078, 8, 0x01, 0x00000300 },
42 { 0x000050, 1, 0x01, 0x00000011 },
43 { 0x000058, 8, 0x01, 0x00000008 },
44 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
Dctxgk104.c35 { 0x001000, 1, 0x01, 0x00000004 },
36 { 0x000039, 3, 0x01, 0x00000000 },
37 { 0x0000a9, 1, 0x01, 0x0000ffff },
38 { 0x000038, 1, 0x01, 0x0fac6881 },
39 { 0x00003d, 1, 0x01, 0x00000001 },
40 { 0x0000e8, 8, 0x01, 0x00000400 },
41 { 0x000078, 8, 0x01, 0x00000300 },
42 { 0x000050, 1, 0x01, 0x00000011 },
43 { 0x000058, 8, 0x01, 0x00000008 },
44 { 0x000208, 8, 0x01, 0x00000001 },
[all …]
Dctxgf100.c37 { 0x001000, 1, 0x01, 0x00000004 },
38 { 0x0000a9, 1, 0x01, 0x0000ffff },
39 { 0x000038, 1, 0x01, 0x0fac6881 },
40 { 0x00003d, 1, 0x01, 0x00000001 },
41 { 0x0000e8, 8, 0x01, 0x00000400 },
42 { 0x000078, 8, 0x01, 0x00000300 },
43 { 0x000050, 1, 0x01, 0x00000011 },
44 { 0x000058, 8, 0x01, 0x00000008 },
45 { 0x000208, 8, 0x01, 0x00000001 },
46 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
/linux-6.12.1/sound/pci/pcxhr/
Dpcxhr_core.c23 #define PCXHR_PLX_OFFSET_MIN 0x40
24 #define PCXHR_PLX_MBOX0 0x40
25 #define PCXHR_PLX_MBOX1 0x44
26 #define PCXHR_PLX_MBOX2 0x48
27 #define PCXHR_PLX_MBOX3 0x4C
28 #define PCXHR_PLX_MBOX4 0x50
29 #define PCXHR_PLX_MBOX5 0x54
30 #define PCXHR_PLX_MBOX6 0x58
31 #define PCXHR_PLX_MBOX7 0x5C
32 #define PCXHR_PLX_L2PCIDB 0x64
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]