23 #define PCXHR_PLX_OFFSET_MIN	0x40
24 #define PCXHR_PLX_MBOX0		0x40
25 #define PCXHR_PLX_MBOX1		0x44
26 #define PCXHR_PLX_MBOX2		0x48
27 #define PCXHR_PLX_MBOX3		0x4C
28 #define PCXHR_PLX_MBOX4		0x50
29 #define PCXHR_PLX_MBOX5		0x54
30 #define PCXHR_PLX_MBOX6		0x58
31 #define PCXHR_PLX_MBOX7		0x5C
32 #define PCXHR_PLX_L2PCIDB	0x64
33 #define PCXHR_PLX_IRQCS		0x68
34 #define PCXHR_PLX_CHIPSC	0x6C
37 #define PCXHR_DSP_ICR		0x00
38 #define PCXHR_DSP_CVR		0x04
39 #define PCXHR_DSP_ISR		0x08
40 #define PCXHR_DSP_IVR		0x0C
41 #define PCXHR_DSP_RXH		0x14
42 #define PCXHR_DSP_TXH		0x14
43 #define PCXHR_DSP_RXM		0x18
44 #define PCXHR_DSP_TXM		0x18
45 #define PCXHR_DSP_RXL		0x1C
46 #define PCXHR_DSP_TXL		0x1C
47 #define PCXHR_DSP_RESET		0x20
48 #define PCXHR_DSP_OFFSET_MAX	0x20
66 #define PCXHR_MBOX0_HF5			(1 << 0)
74 #define PCXHR_CHIPSC_INIT_VALUE		0x100D767E
81 #define PCXHR_ICR_HI08_RREQ		0x01
82 #define PCXHR_ICR_HI08_TREQ		0x02
83 #define PCXHR_ICR_HI08_HDRQ		0x04
84 #define PCXHR_ICR_HI08_HF0		0x08
85 #define PCXHR_ICR_HI08_HF1		0x10
86 #define PCXHR_ICR_HI08_HLEND		0x20
87 #define PCXHR_ICR_HI08_INIT		0x80
89 #define PCXHR_CVR_HI08_HC		0x80
91 #define PCXHR_ISR_HI08_RXDF		0x01
92 #define PCXHR_ISR_HI08_TXDE		0x02
93 #define PCXHR_ISR_HI08_TRDY		0x04
94 #define PCXHR_ISR_HI08_ERR		0x08
95 #define PCXHR_ISR_HI08_CHK		0x10
96 #define PCXHR_ISR_HI08_HREQ		0x80
117 	int i = 0;  in pcxhr_check_reg_bit()
126 			return 0;  in pcxhr_check_reg_bit()
131 		   "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=%x\n",  in pcxhr_check_reg_bit()
140 #define PCXHR_MASK_EXTRA_INFO		0x0000FE
141 #define PCXHR_MASK_IT_HF0		0x000100
142 #define PCXHR_MASK_IT_HF1		0x000200
143 #define PCXHR_MASK_IT_NO_HF0_HF1	0x000400
144 #define PCXHR_MASK_IT_MANAGE_HF5	0x000800
145 #define PCXHR_MASK_IT_WAIT		0x010000
146 #define PCXHR_MASK_IT_WAIT_EXTRA	0x020000
148 #define PCXHR_IT_SEND_BYTE_XILINX	(0x0000003C | PCXHR_MASK_IT_HF0)
149 #define PCXHR_IT_TEST_XILINX		(0x0000003C | PCXHR_MASK_IT_HF1 | \
151 #define PCXHR_IT_DOWNLOAD_BOOT		(0x0000000C | PCXHR_MASK_IT_HF1 | \
154 #define PCXHR_IT_RESET_BOARD_FUNC	(0x0000000C | PCXHR_MASK_IT_HF0 | \
157 #define PCXHR_IT_DOWNLOAD_DSP		(0x0000000C | \
160 #define PCXHR_IT_DEBUG			(0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1)
161 #define PCXHR_IT_RESET_SEMAPHORE	(0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1)
162 #define PCXHR_IT_MESSAGE		(0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1)
163 #define PCXHR_IT_RESET_CHK		(0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1)
164 #define PCXHR_IT_UPDATE_RBUFFER		(0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1)
178 	if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) {  in pcxhr_send_it_dsp()
203 	/* wait for CVR_HI08_HC == 0 */  in pcxhr_send_it_dsp()
204 	err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_CVR,  PCXHR_CVR_HI08_HC, 0,  in pcxhr_send_it_dsp()
223 	return 0; /* retry not handled here */  in pcxhr_send_it_dsp()
247 	pcxhr_enable_irq(mgr, 0);  in pcxhr_reset_dsp()
250 	PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 0);  in pcxhr_reset_dsp()
256 	PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, 0);  in pcxhr_reset_dsp()
284 		if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) {  in pcxhr_load_xilinx_binary()
294 	for (i = 0; i < xilinx->size; i++, image++) {  in pcxhr_load_xilinx_binary()
296 		mask = 0x80;  in pcxhr_load_xilinx_binary()
314 	return 0;  in pcxhr_load_xilinx_binary()
328 	if (dsp->size <= 0)  in pcxhr_download_dsp()
335 	for (i = 0; i < dsp->size; i += 3) {  in pcxhr_download_dsp()
337 		if (i == 0) {  in pcxhr_download_dsp()
339 			len = (unsigned int)((data[0]<<16) +  in pcxhr_download_dsp()
356 		PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, data[0]);  in pcxhr_download_dsp()
365 	return 0;  in pcxhr_download_dsp()
388 		return 0;  in pcxhr_load_eeprom_binary()
410 	if (snd_BUG_ON(physaddr & 0xff))  in pcxhr_load_boot_binary()
414 	err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_BOOT, 0);  in pcxhr_load_boot_binary()
436 	err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_BOARD_FUNC, 0);  in pcxhr_load_dsp_binary()
439 	err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_DSP, 0);  in pcxhr_load_dsp_binary()
461 	RMH_SSIZE_FIXED = 0,	/* status size fix (st_length = 0..x) */
470 [CMD_VERSION] =				{ 0x010000, 1, RMH_SSIZE_FIXED },
471 [CMD_SUPPORTED] =			{ 0x020000, 4, RMH_SSIZE_FIXED },
472 [CMD_TEST_IT] =				{ 0x040000, 1, RMH_SSIZE_FIXED },
473 [CMD_SEND_IRQA] =			{ 0x070001, 0, RMH_SSIZE_FIXED },
474 [CMD_ACCESS_IO_WRITE] =			{ 0x090000, 1, RMH_SSIZE_ARG },
475 [CMD_ACCESS_IO_READ] =			{ 0x094000, 1, RMH_SSIZE_ARG },
476 [CMD_ASYNC] =				{ 0x0a0000, 1, RMH_SSIZE_ARG },
477 [CMD_MODIFY_CLOCK] =			{ 0x0d0000, 0, RMH_SSIZE_FIXED },
478 [CMD_RESYNC_AUDIO_INPUTS] =		{ 0x0e0000, 0, RMH_SSIZE_FIXED },
479 [CMD_GET_DSP_RESOURCES] =		{ 0x100000, 4, RMH_SSIZE_FIXED },
480 [CMD_SET_TIMER_INTERRUPT] =		{ 0x110000, 0, RMH_SSIZE_FIXED },
481 [CMD_RES_PIPE] =			{ 0x400000, 0, RMH_SSIZE_FIXED },
482 [CMD_FREE_PIPE] =			{ 0x410000, 0, RMH_SSIZE_FIXED },
483 [CMD_CONF_PIPE] =			{ 0x422101, 0, RMH_SSIZE_FIXED },
484 [CMD_STOP_PIPE] =			{ 0x470004, 0, RMH_SSIZE_FIXED },
485 [CMD_PIPE_SAMPLE_COUNT] =		{ 0x49a000, 2, RMH_SSIZE_FIXED },
486 [CMD_CAN_START_PIPE] =			{ 0x4b0000, 1, RMH_SSIZE_FIXED },
487 [CMD_START_STREAM] =			{ 0x802000, 0, RMH_SSIZE_FIXED },
488 [CMD_STREAM_OUT_LEVEL_ADJUST] =		{ 0x822000, 0, RMH_SSIZE_FIXED },
489 [CMD_STOP_STREAM] =			{ 0x832000, 0, RMH_SSIZE_FIXED },
490 [CMD_UPDATE_R_BUFFERS] =		{ 0x840000, 0, RMH_SSIZE_FIXED },
491 [CMD_FORMAT_STREAM_OUT] =		{ 0x860000, 0, RMH_SSIZE_FIXED },
492 [CMD_FORMAT_STREAM_IN] =		{ 0x870000, 0, RMH_SSIZE_FIXED },
493 [CMD_STREAM_SAMPLE_COUNT] =		{ 0x902000, 2, RMH_SSIZE_FIXED },
494 [CMD_AUDIO_LEVEL_ADJUST] =		{ 0xc22000, 0, RMH_SSIZE_FIXED },
495 [CMD_GET_TIME_CODE] =			{ 0x060000, 5, RMH_SSIZE_FIXED },
496 [CMD_MANAGE_SIGNAL] =			{ 0x0f0000, 0, RMH_SSIZE_FIXED },
545 	for (i = 0; i < rmh->stat_len; i++) {  in pcxhr_read_rmh_status()
566 					rmh->stat_len = (data & 0x0000ff) + 1;  in pcxhr_read_rmh_status()
567 					data &= 0xffff00;  in pcxhr_read_rmh_status()
592 	return 0;  in pcxhr_read_rmh_status()
619 	/* wait for chk bit == 0*/  in pcxhr_send_msg_nolock()
620 	err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, 0,  in pcxhr_send_msg_nolock()
625 	data = rmh->cmd[0];  in pcxhr_send_msg_nolock()
628 		data |= 0x008000;	/* MASK_MORE_THAN_1_WORD_COMMAND */  in pcxhr_send_msg_nolock()
630 		data &= 0xff7fff;	/* MASK_1_WORD_COMMAND */  in pcxhr_send_msg_nolock()
633 		dev_dbg(&mgr->pci->dev, "MSG cmd[0]=%x (%s)\n",  in pcxhr_send_msg_nolock()
641 	PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);  in pcxhr_send_msg_nolock()
642 	PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);  in pcxhr_send_msg_nolock()
643 	PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));  in pcxhr_send_msg_nolock()
654 		PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);  in pcxhr_send_msg_nolock()
655 		PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);  in pcxhr_send_msg_nolock()
656 		PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));  in pcxhr_send_msg_nolock()
672 			PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);  in pcxhr_send_msg_nolock()
673 			PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);  in pcxhr_send_msg_nolock()
674 			PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));  in pcxhr_send_msg_nolock()
698 		dev_err(&mgr->pci->dev, "ERROR RMH(%d): 0x%x\n",  in pcxhr_send_msg_nolock()
706 	if (pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_SEMAPHORE, 1) < 0)  in pcxhr_send_msg_nolock()
721 	rmh->cmd[0] = pcxhr_dsp_cmds[cmd].opcode;  in pcxhr_init_rmh()
735 		rmh->cmd[0] |= 0x800;		/* COMMAND_RECORD_MASK */  in pcxhr_set_pipe_cmd_params()
737 		rmh->cmd[0] |= (param1 << FIELD_SIZE);  in pcxhr_set_pipe_cmd_params()
740 		rmh->cmd[0] |= param2;  in pcxhr_set_pipe_cmd_params()
753  * returns 0 if successful, or a negative error code.
773 	start_mask &= 0xffffff;  in pcxhr_pipes_running()
774 	dev_dbg(&mgr->pci->dev, "CMD_PIPE_STATE MBOX2=0x%06x\n", start_mask);  in pcxhr_pipes_running()
786 	int audio = 0;  in pcxhr_prepair_pipe_start()
788 	*retry = 0;  in pcxhr_prepair_pipe_start()
794 				pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0);  in pcxhr_prepair_pipe_start()
799 						0, 0);  in pcxhr_prepair_pipe_start()
812 			if (rmh.stat[0] == 0)  in pcxhr_prepair_pipe_start()
818 	return 0;  in pcxhr_prepair_pipe_start()
825 	int audio = 0;  in pcxhr_stop_pipes()
832 				pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0);  in pcxhr_stop_pipes()
837 						0, 0);  in pcxhr_stop_pipes()
850 	return 0;  in pcxhr_stop_pipes()
857 	int audio = 0;  in pcxhr_toggle_pipes()
863 				pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0,  in pcxhr_toggle_pipes()
866 				pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0,  in pcxhr_toggle_pipes()
888 	return 0;  in pcxhr_toggle_pipes()
915 		for (i = 0; i < MAX_WAIT_FOR_DSP; i++) {  in pcxhr_set_pipe_state()
919 			if (state == 0)  in pcxhr_set_pipe_state()
926 	if (audio_mask == 0)  in pcxhr_set_pipe_state()
927 		return 0;  in pcxhr_set_pipe_state()
933 	i = 0;  in pcxhr_set_pipe_state()
937 		if ((state & audio_mask) == (start ? audio_mask : 0))  in pcxhr_set_pipe_state()
956 	return 0;  in pcxhr_set_pipe_state()
971 			*changed = 0;  in pcxhr_write_io_num_reg_cont()
973 		return 0;	/* already programmed */  in pcxhr_write_io_num_reg_cont()
976 	rmh.cmd[0] |= IO_NUM_REG_CONT;  in pcxhr_write_io_num_reg_cont()
981 	if (err == 0) {  in pcxhr_write_io_num_reg_cont()
991 #define PCXHR_IRQ_TIMER		0x000300
992 #define PCXHR_IRQ_FREQ_CHANGE	0x000800
993 #define PCXHR_IRQ_TIME_CODE	0x001000
994 #define PCXHR_IRQ_NOTIFY	0x002000
995 #define PCXHR_IRQ_ASYNC		0x008000
996 #define PCXHR_IRQ_MASK		0x00bb00
997 #define PCXHR_FATAL_DSP_ERR	0xff0000
1015 	if (err & 0xfff)  in pcxhr_handle_async_err()
1016 		err &= 0xfff;  in pcxhr_handle_async_err()
1018 		err = ((err >> 12) & 0xfff);  in pcxhr_handle_async_err()
1020 		return 0;  in pcxhr_handle_async_err()
1024 	if (err == 0xe01)  in pcxhr_handle_async_err()
1026 	else if (err == 0xe10)  in pcxhr_handle_async_err()
1054 			    err, prmh->stat[0]);  in pcxhr_msg_thread()
1061 		prmh->cmd[0] |= 1;	/* add SEL_ASYNC_EVENTS */  in pcxhr_msg_thread()
1075 			int is_capture = prmh->stat[i] & 0x400000;  in pcxhr_msg_thread()
1078 			if (prmh->stat[i] & 0x800000) {	/* if BIT_END */  in pcxhr_msg_thread()
1091 			for (j = 0; j < nb_stream; j++) {  in pcxhr_msg_thread()
1101 			for (j = 0; j < nb_audio; j++) {  in pcxhr_msg_thread()
1127 				  stream->pipe->first_audio, 0, stream_mask);  in pcxhr_stream_read_position()
1132 		return 0;  in pcxhr_stream_read_position()
1134 	hw_sample_count = ((u_int64_t)rmh.stat[0]) << 24;  in pcxhr_stream_read_position()
1154 		int elapsed = 0;  in pcxhr_update_timer_pos()
1155 		int hardware_read = 0;  in pcxhr_update_timer_pos()
1158 		if (samples_to_add < 0) {  in pcxhr_update_timer_pos()
1159 			stream->timer_is_synced = 0;  in pcxhr_update_timer_pos()
1165 			if ((stream->timer_abs_periods != 0) ||  in pcxhr_update_timer_pos()
1196 				stream->timer_buf_periods = 0;  in pcxhr_update_timer_pos()
1279 		if ((dsp_time_diff < 0) &&  in pcxhr_threaded_irq()
1286 			if (tmp_diff > 0 && tmp_diff <= (2*mgr->granularity)) {  in pcxhr_threaded_irq()
1298 		if (dsp_time_diff == 0)  in pcxhr_threaded_irq()
1314 		for (i = 0; i < mgr->num_cards; i++) {  in pcxhr_threaded_irq()
1316 			for (j = 0; j < chip->nb_streams_capt; j++)  in pcxhr_threaded_irq()
1321 		for (i = 0; i < mgr->num_cards; i++) {  in pcxhr_threaded_irq()
1323 			for (j = 0; j < chip->nb_streams_play; j++)  in pcxhr_threaded_irq()