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/linux-6.12.1/drivers/media/platform/nxp/
Dimx-pxp.h13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c62 #define BPP_INVALID 0
63 #define BPP_BLENDED_PIPE 0xffffffff
397 struct vba_vars_st *v,
716 s = 0; in dscceComputeDelay()
728 if ((ix % w) == 0 && P != 0) in dscceComputeDelay()
731 lstall = 0; in dscceComputeDelay()
741 unsigned int Delay = 0; in dscComputeDelay()
747 Delay = Delay + 0; in dscComputeDelay()
791 Delay = Delay + 0; in dscComputeDelay()
878 unsigned int DPPCycles = 0, DISPCLKCycles = 0; in CalculatePrefetchSchedule()
[all …]
/linux-6.12.1/sound/soc/qcom/
Dlpass-lpaif-reg.h11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ argument
12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) argument
16 #define LPAIF_I2SCTL_LOOPBACK_DISABLE 0
19 #define LPAIF_I2SCTL_SPKEN_DISABLE 0
22 #define LPAIF_I2SCTL_MODE_NONE 0
45 #define LPAIF_I2SCTL_SPKMONO_STEREO 0
48 #define LPAIF_I2SCTL_MICEN_DISABLE 0
53 #define LPAIF_I2SCTL_MICMONO_STEREO 0
56 #define LPAIF_I2SCTL_WSSRC_INTERNAL 0
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddisplay_mode_vba_314.c41 #define BPP_INVALID 0
42 #define BPP_BLENDED_PIPE 0xffffffff
86 #define BPP_INVALID 0
87 #define BPP_BLENDED_PIPE 0xffffffff
708 …unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay,… in dscceComputeDelay()
736 s = 0; in dscceComputeDelay()
748 if ((ix % w) == 0 && P != 0) in dscceComputeDelay()
751 lstall = 0; in dscceComputeDelay()
761 unsigned int Delay = 0; in dscComputeDelay()
767 Delay = Delay + 0; in dscComputeDelay()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c41 #define BPP_INVALID 0
42 #define BPP_BLENDED_PIPE 0xffffffff
88 #define BPP_INVALID 0
89 #define BPP_BLENDED_PIPE 0xffffffff
690 …unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay,… in dscceComputeDelay()
718 s = 0; in dscceComputeDelay()
730 if ((ix % w) == 0 && P != 0) in dscceComputeDelay()
733 lstall = 0; in dscceComputeDelay()
743 unsigned int Delay = 0; in dscComputeDelay()
749 Delay = Delay + 0; in dscComputeDelay()
[all …]
/linux-6.12.1/drivers/media/platform/verisilicon/
Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
Drockchip_vpu2_hw_mpeg2_dec.c23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
[all …]
Dhantro_g1_mpeg2_dec.c25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
[all …]
/linux-6.12.1/drivers/staging/media/sunxi/sun6i-isp/
Dsun6i_isp_reg.h16 #define SUN6I_ISP_SRC_MODE_DRAM 0
19 #define SUN6I_ISP_FE_CFG_REG 0x0
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
24 #define SUN6I_ISP_FE_CTRL_REG 0x4
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
36 #define SUN6I_ISP_FE_INT_EN_REG 0x8
37 #define SUN6I_ISP_FE_INT_EN_FINISH BIT(0)
[all …]
/linux-6.12.1/drivers/pinctrl/mvebu/
Dpinctrl-kirkwood.c19 #define V(f6180, f6190, f6192, f6281, f6282, dx4122, dx1135) \ macro
20 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
25 VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0, 0),
26 VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0, 0),
27 VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0, 0),
28 VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0, 0),
29 VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0, 0),
30 VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1, 0),
31 VARIANT_MV98DX1135 = V(0, 0, 0, 0, 0, 0, 1),
35 MPP_MODE(0,
[all …]
/linux-6.12.1/tools/testing/selftests/bpf/progs/
Dmap_kptr_fail.c27 struct map_value *v; in size_not_bpf_dw() local
28 int key = 0; in size_not_bpf_dw()
30 v = bpf_map_lookup_elem(&array_map, &key); in size_not_bpf_dw()
31 if (!v) in size_not_bpf_dw()
32 return 0; in size_not_bpf_dw()
34 *(u32 *)&v->unref_ptr = 0; in size_not_bpf_dw()
35 return 0; in size_not_bpf_dw()
42 struct map_value *v; in non_const_var_off() local
43 int key = 0, id; in non_const_var_off()
45 v = bpf_map_lookup_elem(&array_map, &key); in non_const_var_off()
[all …]
/linux-6.12.1/drivers/iommu/
Dmsm_iommu_hw-8xxx.h20 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
28 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
29 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
30 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
31 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
35 #define SET_FIELD(addr, mask, shift, v) \ argument
38 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
39 } while (0)
47 #define FL_BASE_MASK 0xFFFFFC00
48 #define FL_TYPE_TABLE (1 << 0)
[all …]
/linux-6.12.1/drivers/iio/adc/
Dstm32-dfsdm.h19 * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
21 * | 0x020 | CHANNEL 1 |
25 * | 0x20 x n | CHANNEL n |
27 * | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
29 * | 0x200 | FILTER 1 |
33 * | 0x100 x m | FILTER m |
37 * | 0x7F0-7FC | Identification registers |
44 #define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
45 #define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
46 #define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
[all …]
/linux-6.12.1/drivers/gpu/host1x/hw/
Dhw_host1x01_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
Dhw_host1x07_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
Dhw_host1x05_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
Dhw_host1x08_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
Dhw_host1x04_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
Dhw_host1x02_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
Dhw_host1x06_uclass.h15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 return 0x0; in host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/aarch64/
Dvgic_init.c21 #define GICR_TYPER 0x8
55 TEST_ASSERT(val == want, "%s; want '0x%x', got '0x%x'", msg, want, val); in v3_redist_reg_get()
61 GUEST_SYNC(0); in guest_code()
70 return __vcpu_run(vcpu) ? -errno : 0; in run_vcpu()
77 struct vm_gic v; in vm_gic_create_with_vcpus() local
79 v.gic_dev_type = gic_dev_type; in vm_gic_create_with_vcpus()
80 v.vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); in vm_gic_create_with_vcpus()
81 v.gic_fd = kvm_create_device(v.vm, gic_dev_type); in vm_gic_create_with_vcpus()
83 return v; in vm_gic_create_with_vcpus()
88 struct vm_gic v; in vm_gic_create_barebones() local
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calc_auto.c40 void scaler_settings_calculation(struct dcn_bw_internal_vars *v) in scaler_settings_calculation() argument
43 for (k = 0; k <= v->number_of_active_planes - 1; k++) { in scaler_settings_calculation()
44 if (v->allow_different_hratio_vratio == dcn_bw_yes) { in scaler_settings_calculation()
45 if (v->source_scan[k] == dcn_bw_hor) { in scaler_settings_calculation()
46 v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k]; in scaler_settings_calculation()
47 v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k]; in scaler_settings_calculation()
50 v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k]; in scaler_settings_calculation()
51 v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k]; in scaler_settings_calculation()
55 if (v->source_scan[k] == dcn_bw_hor) { in scaler_settings_calculation()
56 …v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k… in scaler_settings_calculation()
[all …]
/linux-6.12.1/drivers/md/
Ddm-verity-target.c59 struct dm_verity *v; member
69 * The variable hash_verified is set to 0 when allocating the buffer, then
70 * it can be changed to 1 and it is never reset to 0 again.
88 aux->hash_verified = 0; in dm_bufio_alloc_callback()
94 static sector_t verity_map_sector(struct dm_verity *v, sector_t bi_sector) in verity_map_sector() argument
96 return v->data_start + dm_target_offset(v->ti, bi_sector); in verity_map_sector()
101 * (0 is the lowest level).
105 static sector_t verity_position_at_level(struct dm_verity *v, sector_t block, in verity_position_at_level() argument
108 return block >> (level * v->hash_per_block_bits); in verity_position_at_level()
111 static int verity_ahash_update(struct dm_verity *v, struct ahash_request *req, in verity_ahash_update() argument
[all …]
/linux-6.12.1/drivers/staging/media/sunxi/cedrus/
Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
32 #define VE_ENGINE_DEC_MPEG 0x100
33 #define VE_ENGINE_DEC_H264 0x200
34 #define VE_ENGINE_DEC_H265 0x500
36 #define VE_MODE 0x00
40 #define VE_MODE_REC_WR_MODE_2MB (0x01 << 20)
41 #define VE_MODE_REC_WR_MODE_1MB (0x00 << 20)
42 #define VE_MODE_DDR_MODE_BW_128 (0x03 << 16)
43 #define VE_MODE_DDR_MODE_BW_256 (0x02 << 16)
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/
Dnand_ids.c10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
36 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00} },
[all …]

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