| /linux-6.12.1/arch/xtensa/variants/de212/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 0 /* number of coprocessors */
36 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
40 /* Save area for non-coprocessor optional and custom (TIE) state: */
45 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
58 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
59 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
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| /linux-6.12.1/arch/xtensa/variants/csp/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
43 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
45 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
48 #define XCHAL_CP0_SA_SIZE 0
50 #define XCHAL_CP1_SA_SIZE 0
52 #define XCHAL_CP2_SA_SIZE 0
[all …]
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| /linux-6.12.1/arch/xtensa/variants/test_kc705_be/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
55 #define XCHAL_CP2_SA_SIZE 0
[all …]
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| /linux-6.12.1/tools/testing/selftests/cgroup/ |
| D | test_cpuset_prs.sh | 2 # SPDX-License-Identifier: GPL-2.0
16 [[ $(id -u) -eq 0 ]] || skip_test "Test must be run as root!"
20 WAIT_INOTIFY=$(cd $(dirname $0); pwd)/wait_inotify
23 CGROUP2=$(mount -t cgroup2 | head -1 | awk -e '{print $3}')
24 [[ -n "$CGROUP2" ]] || skip_test "Cgroup v2 mount point not found!"
28 NR_CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")
29 [[ $NR_CPUS -lt 8 ]] && skip_test "Test needs at least 8 cpus available!"
32 if [[ -c /dev/console && -w /dev/console ]]
41 VERBOSE=0
44 while [[ "$1" = -* ]]
[all …]
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| /linux-6.12.1/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
55 #define XCHAL_CP2_SA_SIZE 0
[all …]
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| /linux-6.12.1/tools/testing/selftests/kvm/aarch64/ |
| D | get-reg-list.c | 1 // SPDX-License-Identifier: GPL-2.0
27 ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */
28 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
29 0,
33 ARM64_SYS_REG(3, 0, 10, 2, 2), /* PIRE0_EL1 */
34 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
39 ARM64_SYS_REG(3, 0, 10, 2, 3), /* PIR_EL1 */
40 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
45 ARM64_SYS_REG(3, 0, 10, 2, 4), /* POR_EL1 */
46 ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */
[all …]
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| /linux-6.12.1/drivers/staging/vt6655/ |
| D | rf.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 * IFRFbWriteEmbedded - Embedded write RF register via MAC
37 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
38 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
39 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
40 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
41 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
42 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
43 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
44 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
[all …]
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | sysreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
29 #define Op0_mask 0x3
31 #define Op1_mask 0x7
[all …]
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| /linux-6.12.1/tools/arch/arm64/include/asm/ |
| D | sysreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/gpr-num.h>
21 * [20-19] : Op0
22 * [18-16] : Op1
23 * [15-12] : CRn
24 * [11-8] : CRm
25 * [7-5] : Op2
28 #define Op0_mask 0x3
30 #define Op1_mask 0x7
32 #define CRn_mask 0xf
[all …]
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| /linux-6.12.1/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
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| D | sm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
16 return -ERANGE; in oob_sm_ooblayout_ecc()
18 oobregion->length = 3; in oob_sm_ooblayout_ecc()
19 oobregion->offset = ((section + 1) * 8) - 3; in oob_sm_ooblayout_ecc()
21 return 0; in oob_sm_ooblayout_ecc()
28 case 0: in oob_sm_ooblayout_free()
30 oobregion->offset = 0; in oob_sm_ooblayout_free()
31 oobregion->length = 4; in oob_sm_ooblayout_free()
35 oobregion->offset = 6; in oob_sm_ooblayout_free()
[all …]
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| /linux-6.12.1/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_68xx.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
16 soc@0 {
17 compatible = "simple-bus";
18 #address-cells = <2>;
[all …]
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| D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
6 * use. Because of this, it contains a super-set of the available
13 soc@0 {
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | uncore-cache.json | 3 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
4 "Counter": "0,1,2,3",
5 "EventCode": "0x35",
8 "UMask": "0x18",
12 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ",
13 "Counter": "0,1,2,3",
14 "EventCode": "0x35",
17 "UMask": "0x28",
21 …ries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ",
22 "Counter": "0,1,2,3",
[all …]
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| /linux-6.12.1/drivers/phy/rockchip/ |
| D | phy-rockchip-inno-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
25 /* REG: 0x00 */
26 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
27 /* REG: 0x01 */
30 #define RK3228_BYPASS_PLLPD_EN BIT(0)
31 /* REG: 0x02 */
33 #define RK3228_PDATAEN_DISABLE BIT(0)
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | uncore-memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
31 "UMask": "0x8",
36 "Counter": "0,1,2,3",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | uncore-memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
31 "UMask": "0x8",
36 "Counter": "0,1,2,3",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
32 "UMask": "0x8",
37 "Counter": "0,1,2,3",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | uncore-memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x1",
9 "UMask": "0x8",
14 "Counter": "0,1,2,3",
15 "EventCode": "0x1",
19 "UMask": "0x1",
24 "Counter": "0,1,2,3",
25 "EventCode": "0x1",
29 "UMask": "0x2",
34 "Counter": "0,1,2,3",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-memory.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x4",
10 "UMask": "0x3",
15 "Counter": "0,1,2,3",
16 "EventCode": "0x4",
21 "UMask": "0xc",
26 "Counter": "0,1,2,3",
27 "EventCode": "0x1",
32 "UMask": "0x8",
37 "Counter": "0,1,2,3",
[all …]
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| /linux-6.12.1/arch/m68k/include/asm/ |
| D | bvme6000hw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define BVME_PIT_BASE 0xffa00000
15 pad_a[3], pgcr,
16 pad_b[3], psrr,
17 pad_c[3], paddr,
18 pad_d[3], pbddr,
19 pad_e[3], pcddr,
20 pad_f[3], pivr,
21 pad_g[3], pacr,
22 pad_h[3], pbcr,
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sierraforest/ |
| D | uncore-interconnect.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x17",
17 "UMask": "0x1",
22 "Counter": "0,1,2,3",
23 "EventCode": "0x16",
26 "UMask": "0x1",
31 "Counter": "0,1,2,3",
32 "EventCode": "0x18",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/ |
| D | uncore-interconnect.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x17",
16 "UMask": "0x1",
21 "Counter": "0,1,2,3",
22 "EventCode": "0x16",
25 "UMask": "0x1",
30 "Counter": "0,1,2,3",
31 "EventCode": "0x18",
[all …]
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| /linux-6.12.1/include/dt-bindings/pinctrl/ |
| D | pads-imx8qm.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #define IMX8QM_SIM0_CLK 0
14 #define IMX8QM_SIM0_PD 3
284 #define IMX8QM_SIM0_CLK_DMA_SIM0_CLK IMX8QM_SIM0_CLK 0
285 #define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3
286 #define IMX8QM_SIM0_RST_DMA_SIM0_RST IMX8QM_SIM0_RST 0
287 #define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3
288 #define IMX8QM_SIM0_IO_DMA_SIM0_IO IMX8QM_SIM0_IO 0
289 #define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3
290 #define IMX8QM_SIM0_PD_DMA_SIM0_PD IMX8QM_SIM0_PD 0
[all …]
|