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/linux-6.12.1/drivers/dma/
Dxgene-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Applied Micro X-Gene SoC DMA engine Driver
15 #include <linux/dma-mapping.h>
27 /* X-Gene DMA ring csr registers and bit definations */
44 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
46 ((m) &= (~BIT(31 - (v))))
77 /* X-Gene DMA device csr registers and bit definitions */
106 /* X-Gene SoC EFUSE csr register and bit defination */
110 /* X-Gene DMA Descriptor format */
127 /* X-Gene DMA descriptor empty s/w signature */
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/linux-6.12.1/drivers/dma/sf-pdma/
Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
26 #include "sf-pdma.h"
63 desc->chan = chan; in sf_pdma_alloc_desc()
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Dsf-pdma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
20 #include <linux/dma-direction.h>
23 #include "../virt-dma.h"
36 #define PDMA_ACT_TYPE 0x104 /* Read-only */
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DMakefile1 obj-$(CONFIG_SF_PDMA) += sf-pdma.o
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
26 - $ref: dma-controller.yaml#
31 - enum:
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Dmarvell,mmp-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Duje Mihanović <duje.mihanovic@skole.hr>
18 - marvell,pdma-1.0
19 - marvell,adma-1.0
20 - marvell,pxa910-squ
35 '#dma-channels':
38 '#dma-requests':
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/linux-6.12.1/include/linux/dma/
Dk3-psil.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum udma_tp_level - Channel Throughput Levels
29 * enum psil_endpoint_type - PSI-L Endpoint type
31 * @PSIL_EP_PDMA_XY: XY mode PDMA
32 * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA
33 * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA
43 * struct psil_endpoint_config - PSI-L Endpoint configuration
44 * @ep_type: PSI-L endpoint type
50 * @pdma_acc32: ACC32 must be enabled on the PDMA side
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/linux-6.12.1/Documentation/devicetree/bindings/crypto/
Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
4 - compatible : Should be one of the following strings:
5 "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
6 "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
13 compatible = "axis,artpec6-crypto";
/linux-6.12.1/arch/mips/boot/dts/ingenic/
Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
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Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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/linux-6.12.1/arch/arm/boot/dts/intel/pxa/
Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
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Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 { label
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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Dpxa25x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "dt-bindings/clock/pxa-clock.h"
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
32 clock-output-names = "ostimer";
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Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
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Dpxa2xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
8 #include "dt-bindings/clock/pxa-clock.h"
12 mux- ## func { \
17 mux- ## func { \
20 low-power-disable; \
23 mux- ## func { \
26 low-power-enable; \
30 #address-cells = <1>;
31 #size-cells = <1>;
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/linux-6.12.1/drivers/video/fbdev/riva/
Dnvreg.h3 * Copyright 1996-1997 David J. McKay
30 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
41 #define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
84 #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
85 #define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
86 #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
87 #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
88 #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
89 #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dairoha,en7581-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
14 These SoCs have multi-GMAC ports.
19 - airoha,en7581-eth
23 - description: Frame engine base address
24 - description: QDMA0 base address
25 - description: QDMA1 base address
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/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
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Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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/linux-6.12.1/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
12 #include <linux/dma-mapping.h>
57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
100 /* PDMA HW LRO Alter Flow Timer Register */
136 /* Unicast Filter MAC Address Register - Low */
140 /* Unicast Filter MAC Address Register - High */
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Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
48 .pdma = {
98 .pdma = {
114 .pdma = {
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/linux-6.12.1/arch/mips/ralink/
Dill_acc.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <asm/mach-ralink/ralink_regs.h>
29 "cpu", "dma", "ppe", "pdma rx", "pdma tx", "pci/e", "wmac", "usb",
38 dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n", in ill_acc_irq_handler()
56 if (of_machine_is_compatible("ralink,rt5350-soc")) in ill_acc_of_setup()
57 return -EINVAL; in ill_acc_of_setup()
59 np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc"); in ill_acc_of_setup()
61 return -EINVAL; in ill_acc_of_setup()
67 return -EINVAL; in ill_acc_of_setup()
73 dev_err(&pdev->dev, "failed to get irq\n"); in ill_acc_of_setup()
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/dma/
Dbase.c36 struct nvkm_dma *dma = nvkm_dma(oclass->engine); in nvkm_dma_oclass_new()
40 ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); in nvkm_dma_oclass_new()
42 *pobject = &dmaobj->object; in nvkm_dma_oclass_new()
55 return nvkm_dma_oclass_new(oclass->engine->subdev.device, in nvkm_dma_oclass_fifo_new()
73 sclass->base = oclass[0]; in nvkm_dma_oclass_base_get()
74 sclass->engn = oclass; in nvkm_dma_oclass_base_get()
86 oclass->base = nvkm_dma_sclass[index]; in nvkm_dma_oclass_fifo_get()
107 enum nvkm_subdev_type type, int inst, struct nvkm_dma **pdma) in nvkm_dma_new_() argument
111 if (!(dma = *pdma = kzalloc(sizeof(*dma), GFP_KERNEL))) in nvkm_dma_new_()
112 return -ENOMEM; in nvkm_dma_new_()
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/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7615/
Ddma.c1 // SPDX-License-Identifier: ISC
27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], in mt7622_init_tx_queues_multi()
34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT, in mt7622_init_tx_queues_multi()
40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU, in mt7622_init_tx_queues_multi()
49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL, in mt7615_init_tx_queues()
54 if (!is_mt7615(&dev->mt76)) in mt7615_init_tx_queues()
57 ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE, in mt7615_init_tx_queues()
62 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU, in mt7615_init_tx_queues()
70 dev = mt76_priv(napi->dev); in mt7615_poll_tx()
71 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt7615_poll_tx()
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Dpci.c1 // SPDX-License-Identifier: ISC
42 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in mt7615_pci_probe()
48 map = id->device == 0x7663 ? mt7663e_reg_map : mt7615e_reg_map; in mt7615_pci_probe()
49 ret = mt7615_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0], in mt7615_pci_probe()
50 pdev->irq, map); in mt7615_pci_probe()
67 devm_free_irq(&pdev->dev, pdev->irq, dev); in mt7615_pci_remove()
79 err = mt76_connac_pm_wake(&dev->mphy, &dev->pm); in mt7615_pci_suspend()
83 hif_suspend = !test_bit(MT76_STATE_SUSPEND, &dev->mphy.state) && in mt7615_pci_suspend()
91 napi_disable(&mdev->tx_napi); in mt7615_pci_suspend()
92 mt76_worker_disable(&mdev->tx_worker); in mt7615_pci_suspend()
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