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12

/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See ../reserved-memory/reserved-memory.txt for details.
[all …]
/linux-6.12.1/include/sound/sof/
Ddai-intel.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
39 /* mclk 0 disable */
41 /* mclk 1 disable */
43 /* mclk keep active */
51 /* mclk early start */
55 /* mclk always on */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 uint32_t mclk_rate; /* mclk frequency in Hz */
68 uint32_t fsync_rate; /* fsync frequency in Hz */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
[all …]
/linux-6.12.1/sound/soc/codecs/
Dda9055.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C
58 /* Input - Gain, Select and Filter Registers */
71 /* Output - Gain, Select and Filter Registers */
250 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */
251 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */
252 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */
253 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */
254 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */
255 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */
[all …]
Dwm8988.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8988.c -- WM8988 ALSA SoC audio driver
129 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
137 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
167 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
168 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
169 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
170 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
171 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
180 SOC_ENUM("Treble Cut-off", treble),
[all …]
Dda7210.c1 // SPDX-License-Identifier: GPL-2.0+
11 // Tested on SuperH Ecovec24 board with S16/S24 LE in 48KHz using I2S
223 { 12000000, 2822400, 0xE8, 0x6C, 0x2, 1}, /* MCLK=12Mhz */
224 { 13000000, 2822400, 0xDF, 0x28, 0xC, 1}, /* MCLK=13Mhz */
225 { 13500000, 2822400, 0xDB, 0x0A, 0xD, 1}, /* MCLK=13.5Mhz */
226 { 14400000, 2822400, 0xD4, 0x5A, 0x2, 1}, /* MCLK=14.4Mhz */
227 { 19200000, 2822400, 0xBB, 0x43, 0x9, 1}, /* MCLK=19.2Mhz */
228 { 19680000, 2822400, 0xB9, 0x6D, 0xA, 1}, /* MCLK=19.68Mhz */
229 { 19800000, 2822400, 0xB8, 0xFB, 0xB, 1}, /* MCLK=19.8Mhz */
231 { 12000000, 3072000, 0xF3, 0x12, 0x7, 1}, /* MCLK=12Mhz */
[all …]
Dwm8994.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8994.c -- WM8994 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
77 /* VU bitfields for ADC2, DAC2 not available on WM1811 */
114 struct wm8994 *control = wm8994->wm8994; in wm8958_micd_set_rate()
120 idle = !wm8994->jack_mic; in wm8958_micd_set_rate()
124 sysclk = wm8994->aifclk[1]; in wm8958_micd_set_rate()
126 sysclk = wm8994->aifclk[0]; in wm8958_micd_set_rate()
128 if (control->pdata.micd_rates) { in wm8958_micd_set_rate()
129 rates = control->pdata.micd_rates; in wm8958_micd_set_rate()
[all …]
Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
[all …]
Dcs42l42.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
29 #include <sound/soc-dapm.h>
32 #include <dt-bindings/sound/cs42l42.h>
400 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
401 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
410 switch (ucontrol->value.integer.value[0]) { in cs42l42_slow_start_put()
418 return -EINVAL; in cs42l42_slow_start_put()
426 "1.86Hz", "120Hz", "235Hz", "466Hz"
434 "160Hz", "180Hz", "200Hz", "220Hz",
[all …]
Dcs43130.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs43130.c -- CS43130 ALSA Soc Audio driver
25 #include <sound/soc-dapm.h>
239 dev_dbg(cs43130->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n", in cs43130_pll_config()
240 cs43130->mclk, cs43130->mclk_int); in cs43130_pll_config()
242 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int); in cs43130_pll_config()
244 return -EINVAL; in cs43130_pll_config()
246 if (pll_entry->pll_cal_ratio == 0) { in cs43130_pll_config()
247 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, in cs43130_pll_config()
250 cs43130->pll_bypass = true; in cs43130_pll_config()
[all …]
/linux-6.12.1/sound/soc/stm/
Dstm32_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #include <linux/clk-provider.h>
136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
137 I2S_CGFR_I2SDIV_SHIFT)) - 1)
198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
205 * struct stm32_i2s_data - private data of I2S
214 * @i2smclk: master clock from I2S mclk provider
222 * @mclk_rate: master clock frequency (Hz)
[all …]
/linux-6.12.1/sound/aoa/soundbus/i2sbus/
Dpcm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2sbus driver -- pcm routines
23 *pi = &i2sdev->in; in get_pcm_info()
25 *other = &i2sdev->out; in get_pcm_info()
28 *pi = &i2sdev->out; in get_pcm_info()
30 *other = &i2sdev->in; in get_pcm_info()
34 static int clock_and_divisors(int mclk, int sclk, int rate, int *out) in clock_and_divisors() argument
36 /* sclk must be derived from mclk! */ in clock_and_divisors()
37 if (mclk % sclk) in clock_and_divisors()
38 return -1; in clock_and_divisors()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
30 * doesn't currently care about them / they are always on. The idea
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
[all …]
/linux-6.12.1/drivers/mmc/host/
Dmmci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
47 #define DRIVER_NAME "mmci-pl18x"
377 spin_lock_irqsave(&host->lock, flags); in mmci_card_busy()
378 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) in mmci_card_busy()
380 spin_unlock_irqrestore(&host->lock, flags); in mmci_card_busy()
390 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. in mmci_reg_delay()
[all …]
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
137 /* Max load for eMMC Vdd-io supply */
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
179 u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
[all …]
/linux-6.12.1/drivers/gpu/drm/arm/
Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
32 * check that the hardware can drive the required clock rate, in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid() local
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
39 if (rate != req_rate) { in malidp_crtc_mode_valid()
40 DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n", in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
[all …]
/linux-6.12.1/drivers/iio/adc/
Dad4130.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
125 #define AD4130_INVALID_SLOT -1
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
265 struct clk *mclk; member
393 return -EINVAL; in ad4130_get_reg_size()
[all …]
/linux-6.12.1/sound/soc/mediatek/mt8195/
Dmt8195-dai-etdm.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "mt8195-afe-clk.h"
15 #include "mt8195-afe-common.h"
16 #include "mt8195-reg.h"
99 unsigned int rate; member
117 int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id
123 { .rate = 8000, .reg_value = 0, },
124 { .rate = 12000, .reg_value = 1, },
125 { .rate = 16000, .reg_value = 2, },
126 { .rate = 24000, .reg_value = 3, },
[all …]
/linux-6.12.1/drivers/video/fbdev/aty/
Datyfb_base.c5 * Copyright (C) 1997-2001 Geert Uytterhoeven
10 * - ATI Mach64
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
20 * and on the PowerMac ATI/mach64 display driver:
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
108 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c1 // SPDX-License-Identifier: MIT
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; in dcn32_build_wm_range_table_fpu()
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn32_build_wm_range_table_fpu()
194 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
195 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()
203 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
205 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
[all …]
/linux-6.12.1/arch/mips/cavium-octeon/
Dsetup.c6 * Copyright (C) 2004-2007 Cavium Networks
8 * written by Ralf Baechle <ralf@linux-mips.org>
35 #include <asm/smp-ops.h>
46 #include <asm/octeon/pci-octeon.h>
47 #include <asm/octeon/cvmx-rst-defs.h>
50 * TRUE for devices having registers with little-endian byte
51 * order, FALSE for registers with native-endian byte order.
52 * PCI mandates little-endian, USB and SATA are configuraable,
53 * but we chose little-endian for these.
129 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; in kexec_bootmem_init()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
34 * The decompressor and also some bootloaders rely on a
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Dci_dpm.c169 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
176 struct ci_ps *ps = rps->ps_priv; in ci_get_ps()
185 switch (rdev->pdev->device) { in ci_initialize_powertune_defaults()
193 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
199 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
203 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
207 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
217 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
221 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
223 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
[all …]
/linux-6.12.1/sound/soc/ti/
Ddavinci-mcasp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
37 #include "edma-pcm.h"
38 #include "sdma-pcm.h"
39 #include "udma-pcm.h"
40 #include "davinci-mcasp.h"
114 /* Used for comstraint setting on the second stream */
134 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
141 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
[all …]
/linux-6.12.1/drivers/media/usb/ttusb-budget/
Ddvb-ttusb-budget.c1 // SPDX-License-Identifier: GPL-2.0-or-later
44 we won't support this - yet. it doesn't event support negative filters,
47 datastreams, especially for dvb-net, but hey, that's not my problem.
61 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
87 * since we're casting (struct ttusb*) <-> (struct dvb_demux*) around
123 int mux_state; // 0..2 - MuxSyncWord, 3 - nMuxPacks, 4 - muxpack
130 int cc; /* MuxCounter - will increment on EVERY MUX PACKET */
146 if (mutex_lock_interruptible(&ttusb->semusb) < 0) in ttusb_cmd()
147 return -EAGAIN; in ttusb_cmd()
152 memcpy(data, ttusb->send_buf, len); in ttusb_cmd()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/
Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
[all …]

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