sound/sof/dai-intel.h

1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
39 /* mclk 0 disable */
41 /* mclk 1 disable */
43 /* mclk keep active */
51 /* mclk early start */
55 /* mclk always on */
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
67 	uint32_t mclk_rate;	/* mclk frequency in Hz */
68 	uint32_t fsync_rate;	/* fsync frequency in Hz */
69 	uint32_t bclk_rate;	/* bclk frequency in Hz */
81 	/* MCLK */
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
97 	uint32_t rate;  member
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
105 	uint32_t rate;  member
112 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
155  * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
156  * multi-mode capable and there may be denied mic clock frequencies between
158  * avoid the driver to set clock to an illegal rate.
160  * The duty cycle could be set to 48-52% if not known. Generally these
164  * The microphone clock needs to be usually about 50-80 times the used audio
165  * sample rate. With highest sample rates above 48 kHz this can relaxed
180 	uint32_t pdmclk_min;	/**< Minimum microphone clock in Hz (100000..N) */
181 	uint32_t pdmclk_max;	/**< Maximum microphone clock in Hz (min...N) */
183 	uint32_t fifo_fs;	/**< FIFO sample rate in Hz (8000..96000) */
195 	uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */