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/linux-6.12.1/include/linux/usb/
Dpd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2015-2017 Google, Inc
29 /* 14-15 Reserved */
36 /* 22-31 Reserved */
49 /* 9-14 Reserved */
51 /* 16-31 Reserved */
70 /* 15-31 Reserved */
179 * struct pd_chunked_ext_message_data - PD chunked extended message data as
190 * struct pd_message - PD message as seen on wire
213 #define PDO_TYPE_SHIFT 30
[all …]
/linux-6.12.1/include/dt-bindings/usb/
Dpd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define PDO_TYPE_SHIFT 30
26 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
29 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
32 #define PDO_FIXED(mv, ma, flags) \ argument
34 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
36 #define VSAFE5V 5000 /* mv units */
38 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
39 #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
42 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) argument
[all …]
/linux-6.12.1/drivers/media/v4l2-core/
Dv4l2-vp9.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <media/v4l2-vp9.h>
17 { 137, 30, 42, 148, 151, 207, 70, 52, 91 }, /*left = dc */
20 { 91, 30, 32, 116, 121, 186, 93, 86, 94 }, /*left = d45 */
35 { 52, 30, 74, 113, 130, 175, 51, 64, 58 }, /*left = d207*/
52 { 62, 30, 23, 158, 200, 207, 59, 57, 50 }, /*left = h */
53 { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */
91 { 55, 30, 18, 122, 79, 179, 44, 88, 116 }, /*left = d63 */
96 { 47, 25, 17, 175, 222, 220, 24, 30, 86 }, /*left = h */
99 { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/
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/linux-6.12.1/fs/bcachefs/
Dmean_and_variance_test.c1 // SPDX-License-Identifier: GPL-2.0
44 mean_and_variance_weighted_update(&s, 30, true, 2); in mean_and_variance_weighted_test()
50 mean_and_variance_weighted_update(&s, -10, false, 2); in mean_and_variance_weighted_test()
51 KUNIT_EXPECT_EQ(test, mean_and_variance_weighted_get_mean(s, 2), -10); in mean_and_variance_weighted_test()
54 mean_and_variance_weighted_update(&s, -20, true, 2); in mean_and_variance_weighted_test()
55 KUNIT_EXPECT_EQ(test, mean_and_variance_weighted_get_mean(s, 2), -12); in mean_and_variance_weighted_test()
58 mean_and_variance_weighted_update(&s, -30, true, 2); in mean_and_variance_weighted_test()
59 KUNIT_EXPECT_EQ(test, mean_and_variance_weighted_get_mean(s, 2), -16); in mean_and_variance_weighted_test()
80 for (i = -10; i >= -100; i -= 10) { in mean_and_variance_weighted_advanced_test()
85 KUNIT_EXPECT_EQ(test, mean_and_variance_weighted_get_mean(s, 8), -11); in mean_and_variance_weighted_advanced_test()
[all …]
/linux-6.12.1/drivers/staging/fbtft/
Dfb_hx8353d.c1 // SPDX-License-Identifier: GPL-2.0+
22 par->fbtftops.reset(par); in init_display()
43 /* SLPOUT - Sleep out & booster on */ in init_display()
47 /* DISPON - Display On */ in init_display()
52 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, in init_display()
55 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, in init_display()
58 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, in init_display()
78 #define mv BIT(5) macro
82 * madctl - memory data access control in set_var()
87 * rgb-bgr order color filter panel: 0=rgb, 1=bgr in set_var()
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Dfb_st7735r.c1 // SPDX-License-Identifier: GPL-2.0+
17 "0F 1B 0F 17 33 2C 29 2E 30 30 39 3F 00 07 03 10"
20 -1, MIPI_DCS_SOFT_RESET,
21 -2, 150, /* delay */
23 -1, MIPI_DCS_EXIT_SLEEP_MODE,
24 -2, 500, /* delay */
26 /* FRMCTR1 - frame rate control: normal mode
29 -1, 0xB1, 0x01, 0x2C, 0x2D,
31 /* FRMCTR2 - frame rate control: idle mode
34 -1, 0xB2, 0x01, 0x2C, 0x2D,
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
31 /* 72 */ { 1209886, -36468, 515, 417, -13123, 203},
32 /* 108 */ { 1130804, -27659, 296, 298, -10834, 221},
33 /* 180 */ { 1162871, -27110, 247, 238, -10681, 268},
34 /* 252 */ { 1220458, -28654, 247, 179, -10376, 298},
35 /* 324 */ { 1280953, -30204, 247, 119, -9766, 304},
36 /* 396 */ { 1344547, -31777, 247, 119, -8545, 292},
37 /* 468 */ { 1420168, -34227, 269, 60, -7172, 256},
38 /* 540 */ { 1490757, -35955, 274, 60, -5188, 197},
39 /* 612 */ { 1599112, -42583, 398, 0, -1831, 119},
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu13_driver_if_aldebaran.h68 #define FEATURE_CLK_CG_BIT 30
268 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
269 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
[all …]
Dsmu13_driver_if_v13_0_7.h79 #define FEATURE_FAN_CONTROL_BIT 30
504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
931 uint16_t DcBtcMin; // mV Q2
932 uint16_t DcBtcMax; // mV Q2
[all …]
Dsmu11_driver_if_arcturus.h44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
90 #define FEATURE_SPARE_30_BIT 30
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Dsmu14_driver_if_v14_0.h76 #define FEATURE_GFX_DCS_BIT 30
517 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
520 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
964 uint16_t InitGfx; // In mV(Q2) , should be 0?
965 uint16_t InitSoc; // In mV(Q2)
966 uint16_t InitVddIoMem; // In mV(Q2) MemVdd
967 uint16_t InitVddCiMem; // In mV(Q2) VMemP
1019 uint16_t DcTol; // mV Q2
[all …]
Dsmu11_driver_if_navi10.h50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
51 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
52 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
55 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
58 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
59 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
Dsmu13_driver_if_v13_0_0.h78 #define FEATURE_FAN_CONTROL_BIT 30
503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
922 uint16_t DcBtcMin; // mV Q2
923 uint16_t DcBtcMax; // mV Q2
[all …]
/linux-6.12.1/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
24 #include "cpufreq-dt.h"
47 #define ARMADA_37XX_NB_VDD_EN BIT(30)
58 #define ARMADA_37XX_AVS_ENABLE BIT(30)
77 /* AVS value for the corresponding voltage (in mV) */
166 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
187 * the round-up closest to the target voltage value.
193 /* Find out the round-up closest supported voltage value */ in armada_37xx_avs_val_match()
203 avs = ARRAY_SIZE(avs_map) - 1; in armada_37xx_avs_val_match()
[all …]
Dlonghaul.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2001-2004 Dave Jones.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
192 /* Dummy op - must do something useless after P_LVL3 in do_powersaver()
210 /* Dummy op - must do something useless after P_LVL3 read */ in do_powersaver()
229 /* Dummy op - must do something useless after P_LVL3 in do_powersaver()
261 if (mult == -1) in longhaul_setstate()
262 return -EINVAL; in longhaul_setstate()
266 return -EINVAL; in longhaul_setstate()
[all …]
/linux-6.12.1/drivers/iio/light/
Dcm3605.c1 // SPDX-License-Identifier: GPL-2.0-only
36 * struct cm3605 - CM3605 state
62 IIO_EV_TYPE_THRESH, cm3605->dir); in cm3605_prox_irq()
66 if (cm3605->dir == IIO_EV_DIR_RISING) in cm3605_prox_irq()
67 cm3605->dir = IIO_EV_DIR_FALLING; in cm3605_prox_irq()
69 cm3605->dir = IIO_EV_DIR_RISING; in cm3605_prox_irq()
79 ret = iio_read_channel_processed(cm3605->aout, &res); in cm3605_get_lux()
83 dev_dbg(cm3605->dev, "read %d mV from ADC\n", res); in cm3605_get_lux()
86 * AOUT has an offset of ~30mV then linear at dark in cm3605_get_lux()
88 * (1550 mV) so scale the returned value to this interval in cm3605_get_lux()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/power/supply/
Dmediatek,mt6370-charger.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/mediatek,mt6370-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiaEn Wu <chiaen_wu@richtek.com>
18 const: mediatek,mt6370-charger
34 - description: irq of "USB is plugged in"
35 - description: irq of "BC1.2 is done"
36 - description: irq of "Minimum Input Voltage Regulation loop is active"
38 interrupt-names:
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/linux-6.12.1/drivers/regulator/
Dqcom_rpm-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
16 #include <dt-bindings/mfd/qcom-rpm.h>
27 struct request_member mV; /* used if voltage is in mV */ member
45 (((reg)->parts->fm.mask >> (reg)->parts->fm.shift) == 3)
67 .mV = { 0, 0x00000FFF, 0 },
71 .pf = { 0, 0xC0000000, 30 },
78 .mV = { 0, 0x00000FFF, 0 },
82 .pf = { 0, 0xC0000000, 30 },
100 .mV = { 0, 0x00000FFF, 0 },
[all …]
Dbd71815-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
4 // bd71815-regulator.c ROHM BD71815 regulator driver
21 #include <linux/mfd/rohm-generic.h>
22 #include <linux/mfd/rohm-bd71815.h>
31 10, 20, 30, 50, 70, 100, 200, 300, 500, 700, 1000, 2000, 3000, 4000,
179 return rohm_regulator_set_dvs_levels(data->dvs, np, desc, cfg->regmap); in set_hw_dvs_levels()
185 * by a control bit in register - or by HW state. If HW state specific voltages
186 * are given - then we assume HW state based control should be used.
188 * If volatge value is updated to currently selected register - then output
203 if (of_property_present(np, "rohm,dvs-run-voltage") || in buck12_set_hw_dvs_levels()
[all …]
/linux-6.12.1/drivers/media/pci/tw5864/
Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
92 /* MV Vector Valid */
94 /* MV Flag Valid */
147 /* DDR-DPR Burst Read Enable */
[all …]
Dtw5864-video.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TW5864 driver - video encoding functions
10 #include <media/v4l2-common.h>
11 #include <media/v4l2-event.h>
12 #include <media/videobuf2-dma-contig.h>
15 #include "tw5864-reg.h"
188 return sizes[0] < H264_VLC_BUF_SIZE ? -EINVAL : 0; in tw5864_queue_setup()
199 struct vb2_queue *vq = vb->vb2_queue; in tw5864_buf_queue()
204 spin_lock_irqsave(&dev->slock, flags); in tw5864_buf_queue()
205 list_add_tail(&buf->list, &dev->active); in tw5864_buf_queue()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dtlv320adc3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
8 // Copyright (C) 2014-2018, Ambarella, Inc.
15 #include <dt-bindings/sound/tlv320adc3xxx.h>
33 #include <sound/soc-dapm.h>
59 * Setting the clock source using simple-card (clocks or
60 * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO.
78 /* 2-3 Reserved */
86 /* 9-17 Reserved */
93 /* 23-24 Reserved */
100 #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30)
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_ddi_buf_trans.c1 // SPDX-License-Identifier: MIT
53 /* Idx NT mV d T mV d db */
126 /* Idx NT mV d T mV df db */
362 /* Idx NT mV diff db */
381 /* Idx NT mV diff db */
399 /* BSpec has 2 recommended values - entries 0 and 8.
403 /* Idx NT mV diff db */
419 .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
424 /* NT mV Trans mV db */
443 /* NT mV Trans mV db */
[all …]
/linux-6.12.1/drivers/hwmon/pmbus/
Dadm1275.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Hardware monitoring driver for Analog Devices ADM1275 Hot-Swap Controller
116 [0] = { 27169, 0, -1 }, /* voltage */
117 [1] = { 806, 20475, -1 }, /* current, irange25 */
118 [2] = { 404, 20475, -1 }, /* current, irange50 */
119 [3] = { 8549, 0, -1 }, /* power, irange25 */
120 [4] = { 4279, 0, -1 }, /* power, irange50 */
124 [0] = { 6770, 0, -2 }, /* voltage, vrange 60V */
125 [1] = { 4062, 0, -2 }, /* voltage, vrange 100V */
126 [2] = { 1326, 20480, -1 }, /* current, vsense range 15mV */
[all …]

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