2  * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
31 	/*  72 */ { 1209886, -36468,  515,   417, -13123,  203},
32 	/* 108 */ { 1130804, -27659,  296,   298, -10834,  221},
33 	/* 180 */ { 1162871, -27110,  247,   238, -10681,  268},
34 	/* 252 */ { 1220458, -28654,  247,   179, -10376,  298},
35 	/* 324 */ { 1280953, -30204,  247,   119,  -9766,  304},
36 	/* 396 */ { 1344547, -31777,  247,   119,  -8545,  292},
37 	/* 468 */ { 1420168, -34227,  269,    60,  -7172,  256},
38 	/* 540 */ { 1490757, -35955,  274,    60,  -5188,  197},
39 	/* 612 */ { 1599112, -42583,  398,     0,  -1831,  119},
40 	/* 648 */ { 1366986, -16459, -274,     0,  -3204,   72},
41 	/* 684 */ { 1391884, -17078, -274,   -60,  -1526,   30},
42 	/* 708 */ { 1415522, -17497, -274,   -60,   -458,    0},
43 	/* 756 */ { 1464061, -18331, -274,  -119,   1831,  -72},
44 	/* 804 */ { 1524225, -20064, -254,  -119,   4272, -155},
45 	/* 852 */ { 1608418, -21643, -269,     0,    763,  -48},
54 	int mv;  in gk20a_volt_get_cvb_voltage()  local
56 	mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale);  in gk20a_volt_get_cvb_voltage()
57 	mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0;  in gk20a_volt_get_cvb_voltage()
58 	return mv;  in gk20a_volt_get_cvb_voltage()
70 	int cvb_mv, mv;  in gk20a_volt_get_cvb_t_voltage()  local
74 	mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 +  in gk20a_volt_get_cvb_t_voltage()
75 		DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);  in gk20a_volt_get_cvb_t_voltage()
76 	mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv;  in gk20a_volt_get_cvb_t_voltage()
77 	return mv;  in gk20a_volt_get_cvb_t_voltage()
84 	int mv;  in gk20a_volt_calc_voltage()  local
86 	mv = gk20a_volt_get_cvb_t_voltage(speedo, -10, 100, 10, coef);  in gk20a_volt_calc_voltage()
87 	mv = DIV_ROUND_UP(mv, v_scale);  in gk20a_volt_calc_voltage()
89 	return mv * 1000;  in gk20a_volt_calc_voltage()
98 	uv = regulator_get_voltage(volt->vdd);  in gk20a_volt_vid_get()
100 	for (i = 0; i < volt->base.vid_nr; i++)  in gk20a_volt_vid_get()
101 		if (volt->base.vid[i].uv >= uv)  in gk20a_volt_vid_get()
104 	return -EINVAL;  in gk20a_volt_vid_get()
111 	struct nvkm_subdev *subdev = &volt->base.subdev;  in gk20a_volt_vid_set()
113 	nvkm_debug(subdev, "set voltage as %duv\n", volt->base.vid[vid].uv);  in gk20a_volt_vid_set()
114 	return regulator_set_voltage(volt->vdd, volt->base.vid[vid].uv, 1200000);  in gk20a_volt_vid_set()
121 	struct nvkm_subdev *subdev = &volt->base.subdev;  in gk20a_volt_set_id()
122 	int prev_uv = regulator_get_voltage(volt->vdd);  in gk20a_volt_set_id()
123 	int target_uv = volt->base.vid[id].uv;  in gk20a_volt_set_id()
131 		ret = gk20a_volt_vid_set(&volt->base, volt->base.vid[id].vid);  in gk20a_volt_set_id()
151 	struct nvkm_device_tegra *tdev = device->func->tegra(device);  in gk20a_volt_ctor()
154 	nvkm_volt_ctor(&gk20a_volt, device, type, inst, &volt->base);  in gk20a_volt_ctor()
156 	uv = regulator_get_voltage(tdev->vdd);  in gk20a_volt_ctor()
157 	nvkm_debug(&volt->base.subdev, "the default voltage is %duV\n", uv);  in gk20a_volt_ctor()
159 	volt->vdd = tdev->vdd;  in gk20a_volt_ctor()
161 	volt->base.vid_nr = nb_coefs;  in gk20a_volt_ctor()
162 	for (i = 0; i < volt->base.vid_nr; i++) {  in gk20a_volt_ctor()
163 		volt->base.vid[i].vid = i;  in gk20a_volt_ctor()
164 		volt->base.vid[i].uv = max(  in gk20a_volt_ctor()
165 			gk20a_volt_calc_voltage(&coefs[i], tdev->gpu_speedo),  in gk20a_volt_ctor()
167 		nvkm_debug(&volt->base.subdev, "%2d: vid=%d, uv=%d\n", i,  in gk20a_volt_ctor()
168 			   volt->base.vid[i].vid, volt->base.vid[i].uv);  in gk20a_volt_ctor()
181 		return -ENOMEM;  in gk20a_volt_new()
182 	*pvolt = &volt->base;  in gk20a_volt_new()