161 					      uint32_t offset,  in hif_reg_write_result_check()  argument
166 	value = qdf_ioread32(sc->mem + offset);  in hif_reg_write_result_check()
171 			offset);  in hif_reg_write_result_check()
188 void hif_select_window_confirm(struct hif_pci_softc *sc, uint32_t offset)  in hif_select_window_confirm()  argument
190 	uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;  in hif_select_window_confirm()
201 void hif_select_window_confirm(struct hif_pci_softc *sc, uint32_t offset)  in hif_select_window_confirm()  argument
203 	uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;  in hif_select_window_confirm()
269 	uint32_t offset = addr - sc->mem;  in hif_write32_mb_reg_window()  local
273 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hif_write32_mb_reg_window()
277 		hif_select_window_confirm(sc, offset);  in hif_write32_mb_reg_window()
279 			  (offset & WINDOW_RANGE_MASK), value);  in hif_write32_mb_reg_window()
288 	uint32_t offset = addr - sc->mem;  in hif_read32_mb_reg_window()  local
292 	    offset < MAX_UNWINDOWED_ADDRESS) {  in hif_read32_mb_reg_window()
296 	hif_select_window_confirm(sc, offset);  in hif_read32_mb_reg_window()
298 		       (offset & WINDOW_RANGE_MASK));  in hif_read32_mb_reg_window()
306 #define A_TARGET_READ(scn, offset) \  argument
307 	hif_reg_window_read(scn, offset)
308 #define A_TARGET_WRITE(scn, offset, value) \  argument
309 	hif_reg_window_write(scn, offset, value)
312 					uint32_t offset);
313 void hif_target_write_checked(struct hif_softc *scn, uint32_t offset,
316 #define A_TARGET_READ(scn, offset) \  argument
317 	hif_target_read_checked(scn, (offset))
318 #define A_TARGET_WRITE(scn, offset, value) \  argument
319 	hif_target_write_checked(scn, (offset), (value))
321 #define A_TARGET_READ(scn, offset) \  argument
322 	hif_read32_mb(scn, scn->mem + (offset))
323 #define A_TARGET_WRITE(scn, offset, value) \  argument
324 	hif_write32_mb(scn, (scn->mem) + (offset), value)