Lines Matching defs:ath12k_hw_regs
285 struct ath12k_hw_regs { struct
286 u32 hal_tcl1_ring_id;
287 u32 hal_tcl1_ring_misc;
288 u32 hal_tcl1_ring_tp_addr_lsb;
289 u32 hal_tcl1_ring_tp_addr_msb;
290 u32 hal_tcl1_ring_consumer_int_setup_ix0;
291 u32 hal_tcl1_ring_consumer_int_setup_ix1;
292 u32 hal_tcl1_ring_msi1_base_lsb;
293 u32 hal_tcl1_ring_msi1_base_msb;
294 u32 hal_tcl1_ring_msi1_data;
295 u32 hal_tcl_ring_base_lsb;
297 u32 hal_tcl_status_ring_base_lsb;
299 u32 hal_wbm_idle_ring_base_lsb;
300 u32 hal_wbm_idle_ring_misc_addr;
301 u32 hal_wbm_r0_idle_list_cntl_addr;
302 u32 hal_wbm_r0_idle_list_size_addr;
303 u32 hal_wbm_scattered_ring_base_lsb;
304 u32 hal_wbm_scattered_ring_base_msb;
305 u32 hal_wbm_scattered_desc_head_info_ix0;
306 u32 hal_wbm_scattered_desc_head_info_ix1;
307 u32 hal_wbm_scattered_desc_tail_info_ix0;
308 u32 hal_wbm_scattered_desc_tail_info_ix1;
309 u32 hal_wbm_scattered_desc_ptr_hp_addr;
311 u32 hal_wbm_sw_release_ring_base_lsb;
312 u32 hal_wbm_sw1_release_ring_base_lsb;
313 u32 hal_wbm0_release_ring_base_lsb;
314 u32 hal_wbm1_release_ring_base_lsb;
316 u32 pcie_qserdes_sysclk_en_sel;
317 u32 pcie_pcs_osc_dtct_config_base;
319 u32 hal_ppe_rel_ring_base;
321 u32 hal_reo2_ring_base;
322 u32 hal_reo1_misc_ctrl_addr;
323 u32 hal_reo1_sw_cookie_cfg0;
324 u32 hal_reo1_sw_cookie_cfg1;
325 u32 hal_reo1_qdesc_lut_base0;
326 u32 hal_reo1_qdesc_lut_base1;
327 u32 hal_reo1_ring_base_lsb;
328 u32 hal_reo1_ring_base_msb;
329 u32 hal_reo1_ring_id;
330 u32 hal_reo1_ring_misc;
331 u32 hal_reo1_ring_hp_addr_lsb;
332 u32 hal_reo1_ring_hp_addr_msb;
333 u32 hal_reo1_ring_producer_int_setup;
334 u32 hal_reo1_ring_msi1_base_lsb;
335 u32 hal_reo1_ring_msi1_base_msb;
336 u32 hal_reo1_ring_msi1_data;
337 u32 hal_reo1_aging_thres_ix0;
338 u32 hal_reo1_aging_thres_ix1;
339 u32 hal_reo1_aging_thres_ix2;
340 u32 hal_reo1_aging_thres_ix3;
342 u32 hal_reo2_sw0_ring_base;
344 u32 hal_sw2reo_ring_base;
345 u32 hal_sw2reo1_ring_base;
347 u32 hal_reo_cmd_ring_base;
349 u32 hal_reo_status_ring_base;