Lines Matching +full:0 +full:xff000
16 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD
17 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
26 #define CPT_DFLT_MAX_RXC_ICB_CNT 0xC0ULL
30 u64 free_sts = 0, busy_sts = 0; \
34 for (e = (e_min), i = 0; e < (e_max); e++, i++) { \
36 if (reg & 0x1) \
39 if (reg & 0x2) \
48 #define MAX_SE GENMASK_ULL(15, 0)
91 dev_err_ratelimited(rvu->dev, "Received CPTAF FLT%d irq : 0x%llx", vec, reg); in cpt_af_flt_intr_handler()
96 case 0: in cpt_af_flt_intr_handler()
106 grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF; in cpt_af_flt_intr_handler()
108 rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), 0x0); in cpt_af_flt_intr_handler()
118 val = val & 0x3; in cpt_af_flt_intr_handler()
119 if (val == 0x1 || val == 0x2) in cpt_af_flt_intr_handler()
151 dev_err_ratelimited(rvu->dev, "Received CPTAF RVU irq : 0x%llx", reg); in rvu_cpt_af_rvu_intr_handler()
165 dev_err_ratelimited(rvu->dev, "Received CPTAF RAS irq : 0x%llx", reg); in rvu_cpt_af_ras_intr_handler()
178 ret = request_irq(pci_irq_vector(rvu->pdev, irq_offs), handler, 0, in rvu_cpt_do_register_interrupt()
187 return 0; in rvu_cpt_do_register_interrupt()
209 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1); in cpt_10k_unregister_interrupts()
210 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1); in cpt_10k_unregister_interrupts()
213 for (i = 0; i < flt_vecs + CPT_10K_AF_RVU_RAS_INT_VEC_CNT; i++) in cpt_10k_unregister_interrupts()
228 offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF; in cpt_unregister_interrupts()
239 for (i = 0; i < CPT_AF_INT_VEC_RVU; i++) in cpt_unregister_interrupts()
240 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), ~0ULL); in cpt_unregister_interrupts()
241 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1); in cpt_unregister_interrupts()
242 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1); in cpt_unregister_interrupts()
244 for (i = 0; i < CPT_AF_INT_VEC_CNT; i++) in cpt_unregister_interrupts()
303 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1); in cpt_10k_register_interrupts()
310 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1); in cpt_10k_register_interrupts()
312 return 0; in cpt_10k_register_interrupts()
323 int i, offs, ret = 0; in cpt_register_interrupts()
326 return 0; in cpt_register_interrupts()
329 offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF; in cpt_register_interrupts()
333 return 0; in cpt_register_interrupts()
353 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), ~0ULL); in cpt_register_interrupts()
361 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1); in cpt_register_interrupts()
368 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1); in cpt_register_interrupts()
370 return 0; in cpt_register_interrupts()
393 for (i = 0; i < rvu->hw->total_pfs; i++) { in get_cpt_pf_num()
394 pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0); in get_cpt_pf_num()
455 if (blkaddr < 0) in rvu_mbox_handler_cpt_lf_alloc()
458 if (req->eng_grpmsk == 0x0) in rvu_mbox_handler_cpt_lf_alloc()
485 for (slot = 0; slot < num_lfs; slot++) { in rvu_mbox_handler_cpt_lf_alloc()
487 if (cptlf < 0) in rvu_mbox_handler_cpt_lf_alloc()
511 return 0; in rvu_mbox_handler_cpt_lf_alloc()
524 return 0; in cpt_lf_free()
526 for (slot = 0; slot < num_lfs; slot++) { in cpt_lf_free()
528 if (cptlf < 0) in cpt_lf_free()
542 return 0; in cpt_lf_free()
579 nix_sel = (blkaddr == BLKADDR_CPT1) ? 1 : 0; in cpt_inline_ipsec_cfg_inbound()
598 rvu_write64(rvu, blkaddr, CPT_AF_ECO, 0x1); in cpt_inline_ipsec_cfg_inbound()
607 rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0), val); in cpt_inline_ipsec_cfg_inbound()
611 return 0; in cpt_inline_ipsec_cfg_inbound()
649 nix_sel = (nix_blkaddr == BLKADDR_NIX0) ? 0 : 1; in cpt_inline_ipsec_cfg_outbound()
656 return 0; in cpt_inline_ipsec_cfg_outbound()
670 if (blkaddr < 0) in rvu_mbox_handler_cpt_inline_ipsec_cfg()
676 if (cptlf < 0) in rvu_mbox_handler_cpt_inline_ipsec_cfg()
705 if (blkaddr < 0) in validate_and_update_reg_offset()
709 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || in validate_and_update_reg_offset()
710 (offset & 0xFF000) == CPT_AF_LFX_CTL2(0)) { in validate_and_update_reg_offset()
714 lf = (offset & 0xFFF) >> 3; in validate_and_update_reg_offset()
725 if (lf < 0) in validate_and_update_reg_offset()
731 *reg_offset = (req->reg_offset & 0xFF000) + (lf << 3); in validate_and_update_reg_offset()
747 switch (offset & 0xFF000) { in validate_and_update_reg_offset()
748 case CPT_AF_EXEX_STS(0): in validate_and_update_reg_offset()
749 case CPT_AF_EXEX_CTL(0): in validate_and_update_reg_offset()
750 case CPT_AF_EXEX_CTL2(0): in validate_and_update_reg_offset()
751 case CPT_AF_EXEX_UCODE_BASE(0): in validate_and_update_reg_offset()
771 if (blkaddr < 0) in rvu_mbox_handler_cpt_rd_wr_register()
791 return 0; in rvu_mbox_handler_cpt_rd_wr_register()
821 rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0)); in get_ctx_pc()
836 u32 e_min = 0, e_max = 0; in get_eng_sts()
840 max_ses = reg & 0xffff; in get_eng_sts()
841 max_ies = (reg >> 16) & 0xffff; in get_eng_sts()
842 max_aes = (reg >> 32) & 0xffff; in get_eng_sts()
849 e_min = 0; in get_eng_sts()
864 if (blkaddr < 0) in rvu_mbox_handler_cpt_sts()
889 return 0; in rvu_mbox_handler_cpt_sts()
895 #define RXC_ACTIVE_LIMIT GENMASK_ULL(11, 0)
931 if (blkaddr < 0) in rvu_mbox_handler_cpt_rxc_time_cfg()
941 return 0; in rvu_mbox_handler_cpt_rxc_time_cfg()
961 if (blkaddr < 0) in rvu_mbox_handler_cpt_lf_reset()
967 if (cptlf < 0) in rvu_mbox_handler_cpt_lf_reset()
980 return 0; in rvu_mbox_handler_cpt_lf_reset()
993 if (blkaddr < 0) in rvu_mbox_handler_cpt_flt_eng_info()
999 for (vec = 0; vec < flt_vecs; vec++) { in rvu_mbox_handler_cpt_flt_eng_info()
1004 block->cpt_flt_eng_map[vec] = 0x0; in rvu_mbox_handler_cpt_flt_eng_info()
1005 block->cpt_rcvrd_eng_map[vec] = 0x0; in rvu_mbox_handler_cpt_flt_eng_info()
1009 return 0; in rvu_mbox_handler_cpt_flt_eng_info()
1042 if (timeout == 0) in cpt_rxc_teardown()
1055 if (timeout == 0) in cpt_rxc_teardown()
1062 #define INFLIGHT GENMASK_ULL(8, 0)
1066 #define DQPTR GENMASK_ULL(19, 0)
1074 int i = 0; in cpt_lf_disable_iqueue()
1077 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0); in cpt_lf_disable_iqueue()
1086 CPT_AF_BAR2_ALIASX(slot, CPT_LF_Q_SIZE)) & 0x7FFF; in cpt_lf_disable_iqueue()
1095 } while ((pending != 0) && (timeout != 0)); in cpt_lf_disable_iqueue()
1097 if (timeout == 0) in cpt_lf_disable_iqueue()
1106 if ((FIELD_GET(INFLIGHT, inprog) == 0) && in cpt_lf_disable_iqueue()
1107 (FIELD_GET(GRB_CNT, inprog) == 0)) { in cpt_lf_disable_iqueue()
1110 i = 0; in cpt_lf_disable_iqueue()
1113 } while ((timeout != 0) && (i < 10)); in cpt_lf_disable_iqueue()
1115 if (timeout == 0) in cpt_lf_disable_iqueue()
1135 rvu_bar2_sel_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); in rvu_cpt_lf_teardown()
1138 return 0; in rvu_cpt_lf_teardown()
1167 *res = 0xFFFF; in cpt_inline_inb_lf_cmd_send()
1183 inst[0] = 0; in cpt_inline_inb_lf_cmd_send()
1186 inst[2] = 0; in cpt_inline_inb_lf_cmd_send()
1189 inst[4] = 0; in cpt_inline_inb_lf_cmd_send()
1190 inst[5] = 0; in cpt_inline_inb_lf_cmd_send()
1191 inst[6] = 0; in cpt_inline_inb_lf_cmd_send()
1198 cpt_idx = (blkaddr == BLKADDR_CPT0) ? 0 : 1; in cpt_inline_inb_lf_cmd_send()
1210 if (*res == 0xFFFF) in cpt_inline_inb_lf_cmd_send()
1216 if (timeout == 0) in cpt_inline_inb_lf_cmd_send()
1224 return 0; in cpt_inline_inb_lf_cmd_send()
1228 #define CTX_CAM_CPTR GENMASK_ULL(45, 0)
1234 int slot = 0, num_lfs; in rvu_cpt_ctx_flush()
1239 if (nix_blkaddr < 0) in rvu_cpt_ctx_flush()
1243 return 0; in rvu_cpt_ctx_flush()
1258 max_ctx_entries = (reg >> 48) & 0xFFF; in rvu_cpt_ctx_flush()
1264 if (num_lfs == 0) { in rvu_cpt_ctx_flush()
1273 for (i = 0; i < max_ctx_entries; i++) { in rvu_cpt_ctx_flush()
1284 rvu_bar2_sel_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); in rvu_cpt_ctx_flush()
1289 return 0; in rvu_cpt_ctx_flush()
1306 /* Set CPT_AF_RXC_CFG1:max_rxc_icb_cnt to 0xc0 to not effect in rvu_cpt_init()
1318 return 0; in rvu_cpt_init()