57 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))  macro
63 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
66 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
77 	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);  in whack_reset()
206 	FW(fecp, grp_hash_table_high, fep->fec.hthi);  in set_multicast_finish()
207 	FW(fecp, grp_hash_table_low, fep->fec.htlo);  in set_multicast_finish()
248 	FW(fecp, addr_low, addrhi);  in restart()
249 	FW(fecp, addr_high, addrlo);  in restart()
254 	FW(fecp, grp_hash_table_high, fep->fec.hthi);  in restart()
255 	FW(fecp, grp_hash_table_low, fep->fec.htlo);  in restart()
260 	FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);  in restart()
262 	FW(fecp, r_cntrl, PKT_MAXBUF_SIZE << 16);  in restart()
264 	FW(fecp, r_hash, PKT_MAXBUF_SIZE);  in restart()
274 	FW(fecp, r_des_start, rx_bd_base_phys);  in restart()
275 	FW(fecp, x_des_start, tx_bd_base_phys);  in restart()
285 	FW(fecp, fun_code, 0x78000000);  in restart()
291 	FW(fecp, mii_speed, fec_inf->mii_speed);  in restart()
296 	FW(fecp, ievent, 0xffc0);  in restart()
298 	FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);  in restart()
300 	FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);	/* MII enable */  in restart()
326 	FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |  in restart()
332 	FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);  in restart()
333 	FW(fecp, r_des_active, 0x01000000);  in restart()
345 	FW(fecp, x_cntrl, 0x01);	/* Graceful transmit stop */  in stop()
355 	FW(fecp, imask, 0);  in stop()
366 	FW(fecp, ievent, FEC_NAPI_EVENT_MSK);  in napi_clear_event_fs()
390 	FW(fecp, r_des_active, 0x01000000);  in rx_bd_done()
398 	FW(fecp, x_des_active, 0x01000000);  in tx_kickstart()
414 	FW(fecp, ievent, int_events);  in clear_int_events()