Lines Matching full:jpeg
53 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_0_0_early_init()
54 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_0_0_early_init()
63 * jpeg_v5_0_0_sw_init - sw init for JPEG block
75 /* JPEG TRAP */ in jpeg_v5_0_0_sw_init()
77 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_0_0_sw_init()
89 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_sw_init()
95 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_0_0_sw_init()
100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_0_0_sw_init()
101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_0_0_sw_init()
107 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block
111 * JPEG suspend and free up sw allocation
128 * jpeg_v5_0_0_hw_init - start and test JPEG block
136 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_hw_init()
158 * Stop the JPEG block, mark ring as not ready any more
166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v5_0_0_hw_fini()
167 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) in jpeg_v5_0_0_hw_fini()
174 * jpeg_v5_0_0_suspend - suspend JPEG block
178 * HW fini and suspend JPEG block
195 * jpeg_v5_0_0_resume - resume JPEG block
199 * Resume firmware and hw init JPEG block
219 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); in jpeg_v5_0_0_disable_clock_gating()
221 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v5_0_0_disable_clock_gating()
224 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v5_0_0_disable_clock_gating()
231 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v5_0_0_enable_clock_gating()
234 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); in jpeg_v5_0_0_enable_clock_gating()
236 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); in jpeg_v5_0_0_enable_clock_gating()
241 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); in jpeg_v5_0_0_enable_clock_gating()
249 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data); in jpeg_v5_0_0_disable_power_gating()
250 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, in jpeg_v5_0_0_disable_power_gating()
254 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, in jpeg_v5_0_0_disable_power_gating()
263 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), in jpeg_v5_0_0_enable_power_gating()
268 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG), in jpeg_v5_0_0_enable_power_gating()
270 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, in jpeg_v5_0_0_enable_power_gating()
283 // JPEG disable CGC in jpeg_engine_5_0_0_dpg_clock_gating_mode()
295 // Turn on All JPEG clocks in jpeg_engine_5_0_0_dpg_clock_gating_mode()
301 // Turn on All JPEG clocks in jpeg_engine_5_0_0_dpg_clock_gating_mode()
308 * jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode
314 * Start JPEG block with dpg mode
318 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
324 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_0_0_start_dpg_mode()
326 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v5_0_0_start_dpg_mode()
329 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
330 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v5_0_0_start_dpg_mode()
361 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v5_0_0_start_dpg_mode()
362 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v5_0_0_start_dpg_mode()
363 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v5_0_0_start_dpg_mode()
365 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v5_0_0_start_dpg_mode()
367 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); in jpeg_v5_0_0_start_dpg_mode()
368 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0); in jpeg_v5_0_0_start_dpg_mode()
369 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v5_0_0_start_dpg_mode()
370 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v5_0_0_start_dpg_mode()
371 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_start_dpg_mode()
377 * jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode
382 * Stop JPEG block with dpg mode
388 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); in jpeg_v5_0_0_stop_dpg_mode()
390 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); in jpeg_v5_0_0_stop_dpg_mode()
394 * jpeg_v5_0_0_start - start JPEG block
398 * Setup and start the JPEG block
402 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_start()
409 r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram); in jpeg_v5_0_0_start()
418 /* JPEG disable CGC */ in jpeg_v5_0_0_start()
422 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v5_0_0_start()
426 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, in jpeg_v5_0_0_start()
430 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), in jpeg_v5_0_0_start()
438 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v5_0_0_start()
439 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v5_0_0_start()
440 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v5_0_0_start()
442 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v5_0_0_start()
444 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); in jpeg_v5_0_0_start()
445 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); in jpeg_v5_0_0_start()
446 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v5_0_0_start()
447 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v5_0_0_start()
448 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_start()
454 * jpeg_v5_0_0_stop - stop JPEG block
458 * stop the JPEG block
469 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), in jpeg_v5_0_0_stop()
498 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); in jpeg_v5_0_0_dec_ring_get_rptr()
515 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v5_0_0_dec_ring_get_wptr()
533 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v5_0_0_dec_ring_set_wptr()
542 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & in jpeg_v5_0_0_is_idle()
553 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v5_0_0_wait_for_idle()
581 if (state == adev->jpeg.cur_state) in jpeg_v5_0_0_set_powergating_state()
590 adev->jpeg.cur_state = state; in jpeg_v5_0_0_set_powergating_state()
607 DRM_DEBUG("IH: JPEG TRAP\n"); in jpeg_v5_0_0_process_interrupt()
611 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v5_0_0_process_interrupt()
676 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs; in jpeg_v5_0_0_set_dec_ring_funcs()
686 adev->jpeg.inst->irq.num_types = 1; in jpeg_v5_0_0_set_irq_funcs()
687 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs; in jpeg_v5_0_0_set_irq_funcs()