Lines Matching full:sdma
3 // drivers/dma/imx-sdma.c
47 /* SDMA registers */
105 * Error bit set in the CCB status field by the SDMA,
150 * 28 Lower WML Event(LWE) SDMA events reg to check for
154 * 29 Higher WML Event(HWE) SDMA events reg to check for
201 * struct sdma_script_start_addrs - SDMA script start pointers
204 * address space of the SDMA engine.
286 * @unused: padding. The SDMA engine expects an array of 128 byte
296 * struct sdma_state_registers - SDMA context for a channel
325 * struct sdma_context_data - sdma context specific to a channel
409 * struct sdma_channel - housekeeping for a SDMA channel
412 * @desc: sdma description including vd and other special member
413 * @sdma: pointer to the SDMA engine for this channel
415 * @direction: transfer type. Needed for setting SDMA script
417 * @peripheral_type: Peripheral type. Needed for setting SDMA script
435 * @data: specific sdma interface structure
449 struct sdma_engine *sdma; member
490 * @magic: "SDMA"
496 * @ram_code_start: offset of SDMA ram image in this firmware image
497 * @ram_code_size: size of SDMA ram image
515 * ecspi ERR009165 fixed should be done in sdma script
542 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
675 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
676 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
677 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
678 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
679 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
680 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
681 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
682 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
683 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
693 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event) in chnenbl_ofs() argument
695 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
702 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership() local
709 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
710 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
711 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
728 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
729 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
730 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
735 static int is_sdma_channel_enabled(struct sdma_engine *sdma, int channel) in is_sdma_channel_enabled() argument
737 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel)); in is_sdma_channel_enabled()
740 static void sdma_enable_channel(struct sdma_engine *sdma, int channel) in sdma_enable_channel() argument
742 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
748 static int sdma_run_channel0(struct sdma_engine *sdma) in sdma_run_channel0() argument
753 sdma_enable_channel(sdma, 0); in sdma_run_channel0()
755 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
758 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
761 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
764 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
770 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size, in sdma_load_script() argument
773 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
779 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
783 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
793 ret = sdma_run_channel0(sdma); in sdma_load_script()
795 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
797 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
804 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable() local
807 u32 chnenbl = chnenbl_ofs(sdma, event); in sdma_event_enable()
809 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
811 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
815 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
818 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG); in sdma_event_enable()
824 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable() local
826 u32 chnenbl = chnenbl_ofs(sdma, event); in sdma_event_disable()
829 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
831 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
843 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc() local
854 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
855 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
856 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
896 * SDMA transaction status by the time the client tasklet is in sdma_update_channel_loop()
903 /* Assign buffer ownership to SDMA */ in sdma_update_channel_loop()
911 * SDMA stops cyclic channel when DMA request triggers a channel and no SDMA in sdma_update_channel_loop()
914 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) { in sdma_update_channel_loop()
915 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel); in sdma_update_channel_loop()
916 sdma_enable_channel(sdmac->sdma, sdmac->channel); in sdma_update_channel_loop()
947 struct sdma_engine *sdma = dev_id; in sdma_int_handler() local
950 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
951 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
957 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
983 * sets the pc of SDMA script according to the peripheral type
988 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc() local
1004 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
1007 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
1008 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
1011 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
1012 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
1015 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
1016 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1019 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
1020 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1023 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
1024 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
1027 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1030 if (sdmac->sdma->drvdata->ecspi_fixed) { in sdma_get_pc()
1031 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1033 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; in sdma_get_pc()
1041 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
1042 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
1045 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
1046 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
1055 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1056 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1059 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1060 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1061 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1065 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1066 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1067 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1070 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
1071 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
1074 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
1077 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
1078 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
1081 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
1084 per_2_emi = sdma->script_addrs->sai_2_mcu_addr; in sdma_get_pc()
1085 emi_2_per = sdma->script_addrs->mcu_2_sai_addr; in sdma_get_pc()
1088 per_2_emi = sdma->script_addrs->i2c_2_mcu_addr; in sdma_get_pc()
1089 emi_2_per = sdma->script_addrs->mcu_2_i2c_addr; in sdma_get_pc()
1093 emi_2_per = sdma->script_addrs->hdmi_dma_addr; in sdma_get_pc()
1097 dev_err(sdma->dev, "Unsupported transfer type %d\n", in sdma_get_pc()
1112 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context() local
1115 struct sdma_context_data *context = sdma->context; in sdma_load_context()
1116 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
1132 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1133 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1134 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1135 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1136 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1137 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1139 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1161 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1163 ret = sdma_run_channel0(sdma); in sdma_load_context()
1165 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1178 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel() local
1181 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1191 * According to NXP R&D team a delay of one BD SDMA cost time in sdma_channel_terminate_work()
1193 * bit, to ensure SDMA core has really been stopped after SDMA in sdma_channel_terminate_work()
1239 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p() local
1266 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1267 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1270 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1271 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1371 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority() local
1379 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1384 static int sdma_request_channel0(struct sdma_engine *sdma) in sdma_request_channel0() argument
1388 if (sdma->iram_pool) in sdma_request_channel0()
1389 sdma->bd0 = gen_pool_dma_alloc(sdma->iram_pool, in sdma_request_channel0()
1391 &sdma->bd0_phys); in sdma_request_channel0()
1393 sdma->bd0 = dma_alloc_coherent(sdma->dev, in sdma_request_channel0()
1395 &sdma->bd0_phys, GFP_NOWAIT); in sdma_request_channel0()
1396 if (!sdma->bd0) { in sdma_request_channel0()
1401 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1402 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1404 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1415 struct sdma_engine *sdma = desc->sdmac->sdma; in sdma_alloc_bd() local
1418 if (sdma->iram_pool) in sdma_alloc_bd()
1419 desc->bd = gen_pool_dma_alloc(sdma->iram_pool, bd_size, &desc->bd_phys); in sdma_alloc_bd()
1421 desc->bd = dma_alloc_coherent(sdma->dev, bd_size, &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1434 struct sdma_engine *sdma = desc->sdmac->sdma; in sdma_free_bd() local
1436 if (sdma->iram_pool) in sdma_free_bd()
1437 gen_pool_free(sdma->iram_pool, (unsigned long)desc->bd, bd_size); in sdma_free_bd()
1439 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, desc->bd_phys); in sdma_free_bd()
1467 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1496 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1499 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1510 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1512 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1519 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources() local
1534 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1535 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1543 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { in sdma_transfer_init()
1544 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); in sdma_transfer_init()
1588 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy() local
1598 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1628 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1645 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg() local
1657 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1669 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1709 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1732 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic() local
1738 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1754 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1781 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1840 struct sdma_engine *sdma = sdmac->sdma; in sdma_config() local
1847 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n", in sdma_config()
1861 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1866 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1938 static void sdma_add_scripts(struct sdma_engine *sdma, in sdma_add_scripts() argument
1942 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1946 if (!sdma->script_number) in sdma_add_scripts()
1947 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1949 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1951 dev_err(sdma->dev, in sdma_add_scripts()
1952 "SDMA script number %d not match with firmware.\n", in sdma_add_scripts()
1953 sdma->script_number); in sdma_add_scripts()
1957 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1964 * script, both uart ram/rom scripts are present in newer sdma in sdma_add_scripts()
1967 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) { in sdma_add_scripts()
1969 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr; in sdma_add_scripts()
1971 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr; in sdma_add_scripts()
1977 struct sdma_engine *sdma = context; in sdma_load_firmware() local
1983 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1999 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
2002 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
2005 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
2008 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
2011 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
2018 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
2019 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
2020 /* download the RAM image for SDMA */ in sdma_load_firmware()
2021 sdma_load_script(sdma, ram_code, in sdma_load_firmware()
2024 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
2025 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
2027 sdma_add_scripts(sdma, addr); in sdma_load_firmware()
2029 sdma->fw_loaded = true; in sdma_load_firmware()
2031 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
2041 static int sdma_event_remap(struct sdma_engine *sdma) in sdma_event_remap() argument
2043 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
2047 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
2057 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
2060 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
2068 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
2076 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2083 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2090 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
2105 static int sdma_get_firmware(struct sdma_engine *sdma, in sdma_get_firmware() argument
2110 ret = firmware_request_nowait_nowarn(THIS_MODULE, fw_name, sdma->dev, in sdma_get_firmware()
2111 GFP_KERNEL, sdma, sdma_load_firmware); in sdma_get_firmware()
2116 static int sdma_init(struct sdma_engine *sdma) in sdma_init() argument
2122 ret = clk_enable(sdma->clk_ipg); in sdma_init()
2125 ret = clk_enable(sdma->clk_ahb); in sdma_init()
2129 if (sdma->drvdata->check_ratio && in sdma_init()
2130 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
2131 sdma->clk_ratio = 1; in sdma_init()
2133 /* Be sure SDMA has not started yet */ in sdma_init()
2134 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2139 if (sdma->iram_pool) in sdma_init()
2140 sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys); in sdma_init()
2142 sdma->channel_control = dma_alloc_coherent(sdma->dev, ccbsize, &ccb_phys, in sdma_init()
2145 if (!sdma->channel_control) { in sdma_init()
2150 sdma->context = (void *)sdma->channel_control + in sdma_init()
2152 sdma->context_phys = ccb_phys + in sdma_init()
2156 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
2157 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
2161 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
2163 ret = sdma_request_channel0(sdma); in sdma_init()
2167 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
2170 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
2173 if (sdma->clk_ratio) in sdma_init()
2174 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2176 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
2178 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
2181 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
2183 clk_disable(sdma->clk_ipg); in sdma_init()
2184 clk_disable(sdma->clk_ahb); in sdma_init()
2189 clk_disable(sdma->clk_ahb); in sdma_init()
2191 clk_disable(sdma->clk_ipg); in sdma_init()
2192 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
2213 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate() local
2214 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
2245 struct sdma_engine *sdma; in sdma_probe() local
2252 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2253 if (!sdma) in sdma_probe()
2256 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2258 sdma->dev = &pdev->dev; in sdma_probe()
2259 sdma->drvdata = of_device_get_match_data(sdma->dev); in sdma_probe()
2265 sdma->regs = devm_platform_ioremap_resource(pdev, 0); in sdma_probe()
2266 if (IS_ERR(sdma->regs)) in sdma_probe()
2267 return PTR_ERR(sdma->regs); in sdma_probe()
2269 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2270 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2271 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2273 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2274 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2275 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2277 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2281 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2286 dev_name(&pdev->dev), sdma); in sdma_probe()
2290 sdma->irq = irq; in sdma_probe()
2292 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2293 if (!sdma->script_addrs) { in sdma_probe()
2299 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2300 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2303 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2304 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2305 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2306 dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask); in sdma_probe()
2308 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2311 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2313 sdmac->sdma = sdma; in sdma_probe()
2322 * because we need it internally in the SDMA driver. This also means in sdma_probe()
2323 * that channel 0 in dmaengine counting matches sdma channel 1. in sdma_probe()
2326 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2330 sdma->iram_pool = of_gen_pool_get(np, "iram", 0); in sdma_probe()
2331 if (sdma->iram_pool) in sdma_probe()
2335 ret = sdma_init(sdma); in sdma_probe()
2339 ret = sdma_event_remap(sdma); in sdma_probe()
2343 if (sdma->drvdata->script_addrs) in sdma_probe()
2344 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2346 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2348 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2349 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2350 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2351 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2352 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2353 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2354 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2355 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2356 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2357 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2358 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2359 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2360 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2361 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2362 sdma->dma_device.copy_align = 2; in sdma_probe()
2363 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2365 platform_set_drvdata(pdev, sdma); in sdma_probe()
2367 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2374 ret = of_dma_controller_register(np, sdma_xlate, sdma); in sdma_probe()
2383 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2384 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2394 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2399 ret = sdma_get_firmware(sdma, fw_name); in sdma_probe()
2407 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2409 kfree(sdma->script_addrs); in sdma_probe()
2411 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2413 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2419 struct sdma_engine *sdma = platform_get_drvdata(pdev); in sdma_remove() local
2422 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2423 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2424 kfree(sdma->script_addrs); in sdma_remove()
2425 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2426 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2429 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2440 .name = "imx-sdma",
2450 MODULE_DESCRIPTION("i.MX SDMA driver");
2452 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2455 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");