dts/canaan/k210.dtsi

27 		#size-cells = <0>;
29 		cpu0: cpu@0 {
32 			reg = <0>;
36 			i-cache-size = <0x8000>;
38 			d-cache-size = <0x8000>;
52 			i-cache-size = <0x8000>;
54 			d-cache-size = <0x8000>;
77 		reg = <0x80000000 0x400000>, /* sram0 4 MiB */
78 		      <0x80400000 0x200000>, /* sram1 2 MiB */
79 		      <0x80600000 0x200000>; /* aisram 2 MiB */
93 			#clock-cells = <0>;
106 			reg = <0x1000 0x1000>;
112 			reg = <0x2000000 0xC000>;
119 			#address-cells = <0>;
120 			compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
121 			reg = <0xC000000 0x4000000>;
130 			reg = <0x38000000 0x1000>;
140 			reg = <0x38001000 0x1000>;
154 			reg = <0x50000000 0x1000>;
162 			snps,priority = <0 1 2 3 4 5>;
164 			snps,block-size = <0x200000 0x200000 0x200000
165 					   0x200000 0x200000 0x200000>;
173 			ranges = <0x50200000 0x50200000 0x200000>;
178 				#size-cells = <0>;
180 				reg = <0x50200000 0x80>;
187 				gpio1_0: gpio-port@0 {
191 					reg = <0>;
201 				reg = <0x50210000 0x100>;
218 				reg = <0x50220000 0x100>;
235 				reg = <0x50230000 0x100>;
253 				reg = <0x50240000 0x100>;
254 				#address-cells = <0>;
255 				#size-cells = <0>;
266 				reg = <0x50250000 0x200>;
276 				reg = <0x50260000 0x200>;
286 				reg = <0x50270000 0x200>;
296 				reg = <0x50280000 0x100>;
307 				reg = <0x50290000 0x100>;
318 				reg = <0x502A0000 0x100>;
329 				reg = <0x502B0000 0x100>;
339 				reg = <0x502D0000 0x14>;
349 				reg = <0x502D0014 0x14>;
359 				reg = <0x502E0000 0x14>;
369 				reg = <0x502E0014 0x114>;
379 				reg = <0x502F0000 0x14>;
389 				reg = <0x502F0014 0x14>;
402 			ranges = <0x50400000 0x50400000 0x40100>;
407 				reg = <0x50400000 0x100>;
417 				reg = <0x50410000 0x100>;
428 				reg = <0x50440000 0x100>;
457 			ranges = <0x52000000 0x52000000 0x2000200>;
462 				#size-cells = <0>;
464 				reg = <0x52000000 0x100>;
478 				#size-cells = <0>;
480 				reg = <0x53000000 0x100>;
494 				#size-cells = <0>;
496 				reg = <0x54000000 0x200>;