Lines Matching +full:0 +full:x4100000
21 #clock-cells = <0>;
39 reg = <0x2000000 0x800>;
150 reg = <0x2001000 0x1000>;
161 reg = <0x2009000 0x400>;
172 reg = <0x2031000 0x400>;
181 #sound-dai-cells = <0>;
187 reg = <0x2033000 0x1000>;
196 #sound-dai-cells = <0>;
202 reg = <0x2034000 0x1000>;
211 #sound-dai-cells = <0>;
217 reg = <0x2050000 0xa0>;
226 reg = <0x20500a0 0x20>;
235 reg = <0x2500000 0x400>;
248 reg = <0x2500400 0x400>;
261 reg = <0x2500800 0x400>;
274 reg = <0x2500c00 0x400>;
287 reg = <0x2501000 0x400>;
300 reg = <0x2501400 0x400>;
315 reg = <0x2502000 0x400>;
323 #size-cells = <0>;
330 reg = <0x2502400 0x400>;
338 #size-cells = <0>;
345 reg = <0x2502800 0x400>;
353 #size-cells = <0>;
360 reg = <0x2502c00 0x400>;
368 #size-cells = <0>;
373 reg = <0x02504000 0x400>;
378 pinctrl-0 = <&can0_pins>;
384 reg = <0x02504400 0x400>;
389 pinctrl-0 = <&can1_pins>;
395 reg = <0x3000000 0x1000>;
402 reg = <0x3000150 0x4>;
414 reg = <0x3002000 0x1000>;
426 reg = <0x3006000 0x1000>;
433 reg = <0x3040000 0x800>;
445 reg = <0x3102000 0x1000>,
446 <0x3103000 0x1000>;
453 dma-ranges = <0 0x40000000 0x80000000>;
461 reg = <0x4020000 0x1000>;
472 #size-cells = <0>;
477 reg = <0x4021000 0x1000>;
488 #size-cells = <0>;
494 reg = <0x4022000 0x1000>;
508 #size-cells = <0>;
514 reg = <0x04025000 0x1000>;
523 #size-cells = <0>;
530 reg = <0x04026000 0x1000>;
539 #size-cells = <0>;
545 reg = <0x4100000 0x400>;
550 extcon = <&usbphy 0>;
551 phys = <&usbphy 0>;
558 reg = <0x4100400 0x100>,
559 <0x4101800 0x100>,
560 <0x4200800 0x100>;
579 reg = <0x4101000 0x100>;
586 phys = <&usbphy 0>;
594 reg = <0x4101400 0x100>;
599 phys = <&usbphy 0>;
607 reg = <0x4200000 0x100>;
622 reg = <0x4200400 0x100>;
635 reg = <0x4500000 0x10000>;
648 #size-cells = <0>;
655 reg = <0x5000000 0x10000>;
664 compatible = "allwinner,sun20i-d1-de2-mixer-0";
665 reg = <0x5100000 0x100000>;
673 #size-cells = <0>;
687 reg = <0x5200000 0x100000>;
695 #size-cells = <0>;
710 reg = <0x5450000 0x1000>;
730 reg = <0x5451000 0x1000>;
736 #phy-cells = <0>;
741 reg = <0x5460000 0x1000>;
753 #size-cells = <0>;
755 tcon_top_mixer0_in: port@0 {
756 reg = <0>;
766 #size-cells = <0>;
768 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
769 reg = <0>;
782 #size-cells = <0>;
793 #size-cells = <0>;
795 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
796 reg = <0>;
822 reg = <0x5461000 0x1000>;
831 #clock-cells = <0>;
835 #size-cells = <0>;
837 tcon_lcd0_in: port@0 {
838 reg = <0>;
840 #size-cells = <0>;
842 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
843 reg = <0>;
856 #size-cells = <0>;
868 reg = <0x5470000 0x1000>;
878 #size-cells = <0>;
880 tcon_tv0_in: port@0 {
881 reg = <0>;
883 #size-cells = <0>;
885 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
886 reg = <0>;
908 reg = <0x7001000 0x1000>;
916 reg = <0x7010000 0x400>;
929 reg = <0x7090000 0x400>;