arm/mm/proc-arm925.S

112 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
113 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
115 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
132 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
135 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
147 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
169 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
173 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
178 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
179 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
200 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
201 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
203 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
204 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
207 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
208 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
210 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
211 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
217 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
249 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
250 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
254 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
270 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
275 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
276 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
296 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
298 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
301 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
305 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
321 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
326 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
341 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
343 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
348 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
378 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
383 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
401 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
405 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
409 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
410 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
412 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
428 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
430 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
444 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
445 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
447 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4