Lines Matching full:clean
22 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
27 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
66 * clean the whole cache, rather than using the individual
143 * Unconditionally clean and invalidate the entire icache.
154 * Clean and invalidate all cache entries in a particular
162 * Clean and invalidate the entire cache.
173 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
186 * Clean and invalidate a range of cache entries in the
207 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
210 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
249 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
270 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
298 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
311 * Clean the specified virtual address range.
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 * Clean and invalidate the specified virtual address range.
341 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
378 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
405 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
428 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
439 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */