dts/st/stih418-b2264.dts

1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 	compatible = "st,stih418-b2264", "st,stih418";
14 		stdout-path = &sbc_serial0;
24 			operating-points-v2 = <&cpu_opp_table>;
25 			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
26 			cpu-release-addr = <0x94100b8>;
29 			operating-points-v2 = <&cpu_opp_table>;
30 			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
31 			cpu-release-addr = <0x94100b8>;
34 			operating-points-v2 = <&cpu_opp_table>;
35 			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
36 			cpu-release-addr = <0x94100b8>;
39 			operating-points-v2 = <&cpu_opp_table>;
40 			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
41 			cpu-release-addr = <0x94100b8>;
45 	cpu_opp_table: opp-table {
46 		compatible = "operating-points-v2";
47 		opp-shared;
50 			opp-hz = /bits/ 64 <300000000>;
51 			opp-microvolt = <784000>;
54 			opp-hz = /bits/ 64 <500000000>;
55 			opp-microvolt = <784000>;
58 			opp-hz = /bits/ 64 <800000000>;
59 			opp-microvolt = <784000>;
62 			opp-hz = /bits/ 64 <1200000000>;
63 			opp-microvolt = <784000>;
66 			opp-hz = /bits/ 64 <1500000000>;
67 			opp-microvolt = <784000>;
77 		compatible = "gpio-leds";
78 		led-green {
80 			default-state = "off";
85 		pin-controller-sbc@961f080 {
87 				rgmii1-0 {
107 	phy-mode = "rgmii";
108 	pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
109 	st,tx-retime-src = "clkgen";
111 	snps,reset-gpio = <&pio0 7 0>;
112 	snps,reset-active-low;
113 	snps,reset-delays-us = <0 10000 1000000>;
120 		st,sata-gen = <2>; /* SATA GEN3 */
121 		st,osc-rdy;