Lines Matching full:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
360 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
499 gcc: clock-controller@900000 { label
500 compatible = "qcom,gcc-ipq8064", "syscon";
556 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
558 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
566 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
580 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
601 clocks = <&gcc USB30_0_MASTER_CLK>;
606 resets = <&gcc USB30_0_MASTER_RESET>;
624 clocks = <&gcc USB30_0_UTMI_CLK>;
634 clocks = <&gcc USB30_0_MASTER_CLK>;
646 clocks = <&gcc USB30_1_MASTER_CLK>;
651 resets = <&gcc USB30_1_MASTER_RESET>;
669 clocks = <&gcc USB30_1_UTMI_CLK>;
679 clocks = <&gcc USB30_1_MASTER_CLK>;
690 clocks = <&gcc SDC3_H_CLK>;
700 clocks = <&gcc SDC1_H_CLK>;
718 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
737 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
754 clocks = <&gcc GSBI1_H_CLK>;
769 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
779 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
792 clocks = <&gcc GSBI2_H_CLK>;
806 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
816 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
829 clocks = <&gcc GSBI4_H_CLK>;
843 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
853 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
866 clocks = <&gcc GSBI6_H_CLK>;
881 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
895 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
910 clocks = <&gcc GSBI7_H_CLK>;
922 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
932 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
948 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
951 resets = <&gcc ADM0_RESET>,
952 <&gcc ADM0_PBUS_RESET>,
953 <&gcc ADM0_C0_RESET>,
954 <&gcc ADM0_C1_RESET>,
955 <&gcc ADM0_C2_RESET>;
966 clocks = <&gcc GSBI5_H_CLK>;
981 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
991 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1004 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1021 clocks = <&gcc PRNG_CLK>;
1032 clocks = <&gcc EBI2_CLK>,
1033 <&gcc EBI2_AON_CLK>;
1051 clocks = <&gcc SATA_PHY_CFG_CLK>;
1084 clocks = <&gcc PCIE_A_CLK>,
1085 <&gcc PCIE_H_CLK>,
1086 <&gcc PCIE_PHY_CLK>,
1087 <&gcc PCIE_AUX_CLK>,
1088 <&gcc PCIE_ALT_REF_CLK>;
1091 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1094 resets = <&gcc PCIE_ACLK_RESET>,
1095 <&gcc PCIE_HCLK_RESET>,
1096 <&gcc PCIE_POR_RESET>,
1097 <&gcc PCIE_PCI_RESET>,
1098 <&gcc PCIE_PHY_RESET>,
1099 <&gcc PCIE_EXT_RESET>;
1145 clocks = <&gcc PCIE_1_A_CLK>,
1146 <&gcc PCIE_1_H_CLK>,
1147 <&gcc PCIE_1_PHY_CLK>,
1148 <&gcc PCIE_1_AUX_CLK>,
1149 <&gcc PCIE_1_ALT_REF_CLK>;
1152 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1155 resets = <&gcc PCIE_1_ACLK_RESET>,
1156 <&gcc PCIE_1_HCLK_RESET>,
1157 <&gcc PCIE_1_POR_RESET>,
1158 <&gcc PCIE_1_PCI_RESET>,
1159 <&gcc PCIE_1_PHY_RESET>,
1160 <&gcc PCIE_1_EXT_RESET>;
1206 clocks = <&gcc PCIE_2_A_CLK>,
1207 <&gcc PCIE_2_H_CLK>,
1208 <&gcc PCIE_2_PHY_CLK>,
1209 <&gcc PCIE_2_AUX_CLK>,
1210 <&gcc PCIE_2_ALT_REF_CLK>;
1213 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1216 resets = <&gcc PCIE_2_ACLK_RESET>,
1217 <&gcc PCIE_2_HCLK_RESET>,
1218 <&gcc PCIE_2_POR_RESET>,
1219 <&gcc PCIE_2_PCI_RESET>,
1220 <&gcc PCIE_2_PHY_RESET>,
1221 <&gcc PCIE_2_EXT_RESET>;
1274 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1275 <&gcc SATA_H_CLK>,
1276 <&gcc SATA_A_CLK>,
1277 <&gcc SATA_RXOOB_CLK>,
1278 <&gcc SATA_PMALIVE_CLK>;
1282 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1304 clocks = <&gcc GMAC_CORE1_CLK>;
1307 resets = <&gcc GMAC_CORE1_RESET>,
1308 <&gcc GMAC_AHB_RESET>;
1328 clocks = <&gcc GMAC_CORE2_CLK>;
1331 resets = <&gcc GMAC_CORE2_RESET>,
1332 <&gcc GMAC_AHB_RESET>;
1352 clocks = <&gcc GMAC_CORE3_CLK>;
1355 resets = <&gcc GMAC_CORE3_RESET>,
1356 <&gcc GMAC_AHB_RESET>;
1376 clocks = <&gcc GMAC_CORE4_CLK>;
1379 resets = <&gcc GMAC_CORE4_RESET>,
1380 <&gcc GMAC_AHB_RESET>;