1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "qdf_types.h"
20 #include "qdf_util.h"
21 #include "qdf_types.h"
22 #include "qdf_lock.h"
23 #include "qdf_mem.h"
24 #include "qdf_nbuf.h"
25 #include "hal_li_hw_headers.h"
26 #include "hal_internal.h"
27 #include "hal_api.h"
28 #include "target_type.h"
29 #include "wcss_version.h"
30 #include "qdf_module.h"
31
32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
33 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
35 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
36 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
37 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
38 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
39 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
40 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
41 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
42 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
43 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
44 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
45 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
46 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
47 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
48 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
49 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
50 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
51 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
52 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
53 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
54 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
55 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
56 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
57 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
58 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
59 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET
60 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
61 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
62 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
63 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
65 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
66 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
67 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
68 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
69 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
71 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
75 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
77 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
79 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
103 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
105 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
107 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
108
109 #include "hal_6390_tx.h"
110 #include "hal_6390_rx.h"
111 #include <hal_generic_api.h>
112 #include "hal_li_rx.h"
113 #include "hal_li_api.h"
114 #include "hal_li_generic_api.h"
115
116 /**
117 * hal_rx_get_rx_fragment_number_6390() - API to retrieve rx fragment number
118 * @buf: Network buffer
119 *
120 * Return: rx fragment number
121 */
122 static
hal_rx_get_rx_fragment_number_6390(uint8_t * buf)123 uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf)
124 {
125 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
126 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
127
128 /* Return first 4 bits as fragment number */
129 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
130 DOT11_SEQ_FRAG_MASK);
131 }
132
133 /**
134 * hal_rx_msdu_end_da_is_mcbc_get_6390() - API to check if pkt is MCBC
135 * from rx_msdu_end TLV
136 * @buf: pointer to the start of RX PKT TLV headers
137 *
138 * Return: da_is_mcbc
139 */
140 static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t * buf)141 hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf)
142 {
143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
144 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
145
146 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
147 }
148
149 /**
150 * hal_rx_msdu_end_sa_is_valid_get_6390() - API to get_6390 the sa_is_valid
151 * bit from rx_msdu_end TLV
152 * @buf: pointer to the start of RX PKT TLV headers
153 *
154 * Return: sa_is_valid bit
155 */
156 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t * buf)157 hal_rx_msdu_end_sa_is_valid_get_6390(uint8_t *buf)
158 {
159 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
160 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
161 uint8_t sa_is_valid;
162
163 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
164
165 return sa_is_valid;
166 }
167
168 /**
169 * hal_rx_msdu_end_sa_idx_get_6390() - API to get_6390 the sa_idx from
170 * rx_msdu_end TLV
171 * @buf: pointer to the start of RX PKT TLV headers
172 *
173 * Return: sa_idx (SA AST index)
174 */
175 static
hal_rx_msdu_end_sa_idx_get_6390(uint8_t * buf)176 uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf)
177 {
178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
179 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
180 uint16_t sa_idx;
181
182 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
183
184 return sa_idx;
185 }
186
187 /**
188 * hal_rx_desc_is_first_msdu_6390() - Check if first msdu
189 * @hw_desc_addr: hardware descriptor address
190 *
191 * Return: 0 - success/ non-zero failure
192 */
hal_rx_desc_is_first_msdu_6390(void * hw_desc_addr)193 static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr)
194 {
195 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
196 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
197
198 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
199 }
200
201 /**
202 * hal_rx_msdu_end_l3_hdr_padding_get_6390() - API to get_6390 the l3_header
203 * padding from rx_msdu_end TLV
204 * @buf: pointer to the start of RX PKT TLV headers
205 *
206 * Return: number of l3 header padding bytes
207 */
hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t * buf)208 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf)
209 {
210 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
211 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
212 uint32_t l3_header_padding;
213
214 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
215
216 return l3_header_padding;
217 }
218
219 /**
220 * hal_rx_encryption_info_valid_6390() - Returns encryption type.
221 * @buf: rx_tlv_hdr of the received packet
222 *
223 * Return: encryption type
224 */
hal_rx_encryption_info_valid_6390(uint8_t * buf)225 static uint32_t hal_rx_encryption_info_valid_6390(uint8_t *buf)
226 {
227 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
228 struct rx_mpdu_start *mpdu_start =
229 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
230 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
231 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
232
233 return encryption_info;
234 }
235
236 /**
237 * hal_rx_print_pn_6390() - Prints the PN of rx packet.
238 * @buf: rx_tlv_hdr of the received packet
239 *
240 * Return: void
241 */
hal_rx_print_pn_6390(uint8_t * buf)242 static void hal_rx_print_pn_6390(uint8_t *buf)
243 {
244 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
245 struct rx_mpdu_start *mpdu_start =
246 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
247 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
248
249 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
250 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
251 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
252 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
253
254 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
255 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
256 }
257
258 /**
259 * hal_rx_msdu_end_first_msdu_get_6390() - API to get first msdu status
260 * from rx_msdu_end TLV
261 * @buf: pointer to the start of RX PKT TLV headers
262 *
263 * Return: first_msdu
264 */
hal_rx_msdu_end_first_msdu_get_6390(uint8_t * buf)265 static uint8_t hal_rx_msdu_end_first_msdu_get_6390(uint8_t *buf)
266 {
267 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
268 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
269 uint8_t first_msdu;
270
271 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
272
273 return first_msdu;
274 }
275
276 /**
277 * hal_rx_msdu_end_da_is_valid_get_6390() - API to check if da is valid
278 * from rx_msdu_end TLV
279 * @buf: pointer to the start of RX PKT TLV headers
280 *
281 * Return: da_is_valid
282 */
hal_rx_msdu_end_da_is_valid_get_6390(uint8_t * buf)283 static uint8_t hal_rx_msdu_end_da_is_valid_get_6390(uint8_t *buf)
284 {
285 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
286 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
287 uint8_t da_is_valid;
288
289 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
290
291 return da_is_valid;
292 }
293
294 /**
295 * hal_rx_msdu_end_last_msdu_get_6390() - API to get last msdu status
296 * from rx_msdu_end TLV
297 * @buf: pointer to the start of RX PKT TLV headers
298 *
299 * Return: last_msdu
300 */
hal_rx_msdu_end_last_msdu_get_6390(uint8_t * buf)301 static uint8_t hal_rx_msdu_end_last_msdu_get_6390(uint8_t *buf)
302 {
303 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
304 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
305 uint8_t last_msdu;
306
307 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
308
309 return last_msdu;
310 }
311
312 /**
313 * hal_rx_get_mpdu_mac_ad4_valid_6390() - Retrieves if mpdu 4th addr is valid
314 * @buf: Network buffer
315 *
316 * Return: value of mpdu 4th address valid field
317 */
hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t * buf)318 static bool hal_rx_get_mpdu_mac_ad4_valid_6390(uint8_t *buf)
319 {
320 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
321 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
322 bool ad4_valid = 0;
323
324 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
325
326 return ad4_valid;
327 }
328
329 /**
330 * hal_rx_mpdu_start_sw_peer_id_get_6390() - Retrieve sw peer_id
331 * @buf: network buffer
332 *
333 * Return: sw peer_id
334 */
hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t * buf)335 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6390(uint8_t *buf)
336 {
337 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
338 struct rx_mpdu_start *mpdu_start =
339 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
340
341 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
342 &mpdu_start->rx_mpdu_info_details);
343 }
344
345 /**
346 * hal_rx_mpdu_get_to_ds_6390() - API to get the tods info
347 * from rx_mpdu_start
348 * @buf: pointer to the start of RX PKT TLV header
349 *
350 * Return: uint32_t(to_ds)
351 */
hal_rx_mpdu_get_to_ds_6390(uint8_t * buf)352 static uint32_t hal_rx_mpdu_get_to_ds_6390(uint8_t *buf)
353 {
354 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
355 struct rx_mpdu_start *mpdu_start =
356 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
357
358 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
359
360 return HAL_RX_MPDU_GET_TODS(mpdu_info);
361 }
362
363 /**
364 * hal_rx_mpdu_get_fr_ds_6390() - API to get the from ds info
365 * from rx_mpdu_start
366 * @buf: pointer to the start of RX PKT TLV header
367 *
368 * Return: uint32_t(fr_ds)
369 */
hal_rx_mpdu_get_fr_ds_6390(uint8_t * buf)370 static uint32_t hal_rx_mpdu_get_fr_ds_6390(uint8_t *buf)
371 {
372 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
373 struct rx_mpdu_start *mpdu_start =
374 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
375
376 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
377
378 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
379 }
380
381 /**
382 * hal_rx_get_mpdu_frame_control_valid_6390() - Retrieves mpdu
383 * frame control valid
384 * @buf: Network buffer
385 *
386 * Return: value of frame control valid field
387 */
hal_rx_get_mpdu_frame_control_valid_6390(uint8_t * buf)388 static uint8_t hal_rx_get_mpdu_frame_control_valid_6390(uint8_t *buf)
389 {
390 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
391 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
392
393 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
394 }
395
396 /**
397 * hal_rx_mpdu_get_addr1_6390() - API to check get address1 of the mpdu
398 * @buf: pointer to the start of RX PKT TLV headera
399 * @mac_addr: pointer to mac address
400 *
401 * Return: success/failure
402 */
hal_rx_mpdu_get_addr1_6390(uint8_t * buf,uint8_t * mac_addr)403 static QDF_STATUS hal_rx_mpdu_get_addr1_6390(uint8_t *buf, uint8_t *mac_addr)
404 {
405 struct __attribute__((__packed__)) hal_addr1 {
406 uint32_t ad1_31_0;
407 uint16_t ad1_47_32;
408 };
409
410 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
411 struct rx_mpdu_start *mpdu_start =
412 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
413
414 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
415 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
416 uint32_t mac_addr_ad1_valid;
417
418 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
419
420 if (mac_addr_ad1_valid) {
421 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
422 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
423 return QDF_STATUS_SUCCESS;
424 }
425
426 return QDF_STATUS_E_FAILURE;
427 }
428
429 /**
430 * hal_rx_mpdu_get_addr2_6390() - API to check get address2 of the mpdu
431 * in the packet
432 * @buf: pointer to the start of RX PKT TLV header
433 * @mac_addr: pointer to mac address
434 *
435 * Return: success/failure
436 */
hal_rx_mpdu_get_addr2_6390(uint8_t * buf,uint8_t * mac_addr)437 static QDF_STATUS hal_rx_mpdu_get_addr2_6390(uint8_t *buf,
438 uint8_t *mac_addr)
439 {
440 struct __attribute__((__packed__)) hal_addr2 {
441 uint16_t ad2_15_0;
442 uint32_t ad2_47_16;
443 };
444
445 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
446 struct rx_mpdu_start *mpdu_start =
447 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
448
449 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
450 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
451 uint32_t mac_addr_ad2_valid;
452
453 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
454
455 if (mac_addr_ad2_valid) {
456 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
457 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
458 return QDF_STATUS_SUCCESS;
459 }
460
461 return QDF_STATUS_E_FAILURE;
462 }
463
464 /**
465 * hal_rx_mpdu_get_addr3_6390() - API to get address3 of the mpdu
466 * in the packet
467 * @buf: pointer to the start of RX PKT TLV header
468 * @mac_addr: pointer to mac address
469 *
470 * Return: success/failure
471 */
hal_rx_mpdu_get_addr3_6390(uint8_t * buf,uint8_t * mac_addr)472 static QDF_STATUS hal_rx_mpdu_get_addr3_6390(uint8_t *buf, uint8_t *mac_addr)
473 {
474 struct __attribute__((__packed__)) hal_addr3 {
475 uint32_t ad3_31_0;
476 uint16_t ad3_47_32;
477 };
478
479 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
480 struct rx_mpdu_start *mpdu_start =
481 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
482
483 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
484 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
485 uint32_t mac_addr_ad3_valid;
486
487 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
488
489 if (mac_addr_ad3_valid) {
490 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
491 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
492 return QDF_STATUS_SUCCESS;
493 }
494
495 return QDF_STATUS_E_FAILURE;
496 }
497
498 /**
499 * hal_rx_mpdu_get_addr4_6390() - API to get address4 of the mpdu
500 * in the packet
501 * @buf: pointer to the start of RX PKT TLV header
502 * @mac_addr: pointer to mac address
503 *
504 * Return: success/failure
505 */
hal_rx_mpdu_get_addr4_6390(uint8_t * buf,uint8_t * mac_addr)506 static QDF_STATUS hal_rx_mpdu_get_addr4_6390(uint8_t *buf, uint8_t *mac_addr)
507 {
508 struct __attribute__((__packed__)) hal_addr4 {
509 uint32_t ad4_31_0;
510 uint16_t ad4_47_32;
511 };
512
513 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
514 struct rx_mpdu_start *mpdu_start =
515 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
516
517 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
518 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
519 uint32_t mac_addr_ad4_valid;
520
521 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
522
523 if (mac_addr_ad4_valid) {
524 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
525 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
526 return QDF_STATUS_SUCCESS;
527 }
528
529 return QDF_STATUS_E_FAILURE;
530 }
531
532 /**
533 * hal_rx_get_mpdu_sequence_control_valid_6390() - Get mpdu sequence
534 * control valid
535 * @buf: Network buffer
536 *
537 * Return: value of sequence control valid field
538 */
hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t * buf)539 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf)
540 {
541 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
542 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
543
544 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
545 }
546
547 /**
548 * hal_rx_is_unicast_6390() - check packet is unicast frame or not.
549 * @buf: pointer to rx pkt TLV.
550 *
551 * Return: true on unicast.
552 */
hal_rx_is_unicast_6390(uint8_t * buf)553 static bool hal_rx_is_unicast_6390(uint8_t *buf)
554 {
555 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
556 struct rx_mpdu_start *mpdu_start =
557 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
558 uint32_t grp_id;
559 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
560
561 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
562 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
563 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
564 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
565
566 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
567 }
568
569 /**
570 * hal_rx_tid_get_6390() - get tid based on qos control valid.
571 * @hal_soc_hdl: hal soc handle
572 * @buf: pointer to rx pkt TLV.
573 *
574 * Return: tid
575 */
hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)576 static uint32_t hal_rx_tid_get_6390(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
577 {
578 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
579 struct rx_mpdu_start *mpdu_start =
580 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
581 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
582 uint8_t qos_control_valid =
583 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
584 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
585 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
586 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
587
588 if (qos_control_valid)
589 return hal_rx_mpdu_start_tid_get_6390(buf);
590
591 return HAL_RX_NON_QOS_TID;
592 }
593
594 /**
595 * hal_rx_hw_desc_get_ppduid_get_6390() - retrieve ppdu id
596 * @rx_tlv_hdr: start address of rx_pkt_tlvs
597 * @rxdma_dst_ring_desc: Rx HW descriptor
598 *
599 * Return: ppdu id
600 */
hal_rx_hw_desc_get_ppduid_get_6390(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)601 static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *rx_tlv_hdr,
602 void *rxdma_dst_ring_desc)
603 {
604 struct rx_mpdu_info *rx_mpdu_info;
605 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
606
607 rx_mpdu_info =
608 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
609
610 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
611 }
612
613 /**
614 * hal_reo_status_get_header_6390() - Process reo desc info
615 * @ring_desc: REO status ring descriptor
616 * @b: tlv type info
617 * @h1: Pointer to hal_reo_status_header where info to be stored
618 *
619 * Return: none.
620 */
hal_reo_status_get_header_6390(hal_ring_desc_t ring_desc,int b,void * h1)621 static void hal_reo_status_get_header_6390(hal_ring_desc_t ring_desc, int b,
622 void *h1)
623 {
624 uint32_t *d = (uint32_t *)ring_desc;
625 uint32_t val1 = 0;
626 struct hal_reo_status_header *h =
627 (struct hal_reo_status_header *)h1;
628
629 /* Offsets of descriptor fields defined in HW headers start
630 * from the field after TLV header
631 */
632 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
633
634 switch (b) {
635 case HAL_REO_QUEUE_STATS_STATUS_TLV:
636 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
637 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
638 break;
639 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
640 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
641 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
642 break;
643 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
644 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
646 break;
647 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
648 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
649 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
650 break;
651 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
652 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
653 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
654 break;
655 case HAL_REO_DESC_THRES_STATUS_TLV:
656 val1 =
657 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
658 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
659 break;
660 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
661 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
662 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
663 break;
664 default:
665 qdf_nofl_err("ERROR: Unknown tlv\n");
666 break;
667 }
668 h->cmd_num =
669 HAL_GET_FIELD(
670 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
671 val1);
672 h->exec_time =
673 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
674 CMD_EXECUTION_TIME, val1);
675 h->status =
676 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
677 REO_CMD_EXECUTION_STATUS, val1);
678 switch (b) {
679 case HAL_REO_QUEUE_STATS_STATUS_TLV:
680 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
681 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
682 break;
683 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
684 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
685 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
686 break;
687 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
688 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
690 break;
691 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
692 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
693 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
694 break;
695 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
696 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
697 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
698 break;
699 case HAL_REO_DESC_THRES_STATUS_TLV:
700 val1 =
701 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
702 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
703 break;
704 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
705 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
706 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
707 break;
708 default:
709 qdf_nofl_err("ERROR: Unknown tlv\n");
710 break;
711 }
712 h->tstamp =
713 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
714 }
715
716 /**
717 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390() - Retrieve qos control
718 * valid bit from the tlv.
719 * @buf: pointer to rx pkt TLV.
720 *
721 * Return: qos control value.
722 */
723 static inline uint32_t
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t * buf)724 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390(uint8_t *buf)
725 {
726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
727 struct rx_mpdu_start *mpdu_start =
728 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
729
730 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
731 &mpdu_start->rx_mpdu_info_details);
732 }
733
734 /**
735 * hal_rx_msdu_end_sa_sw_peer_id_get_6390() - API to get the sa_sw_peer_id
736 * from rx_msdu_end TLV
737 * @buf: pointer to the start of RX PKT TLV headers
738 *
739 * Return: sa_sw_peer_id index
740 */
741 static inline uint32_t
hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t * buf)742 hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf)
743 {
744 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
745 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
746
747 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
748 }
749
750 /**
751 * hal_tx_desc_set_mesh_en_6390() - Set mesh_enable flag in Tx descriptor
752 * @desc: Handle to Tx Descriptor
753 * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
754 * enabling the interpretation of the 'Mesh Control Present' bit
755 * (bit 8) of QoS Control (otherwise this bit is ignored),
756 * For native WiFi frames, this indicates that a 'Mesh Control' field
757 * is present between the header and the LLC.
758 *
759 * Return: void
760 */
761 static inline
hal_tx_desc_set_mesh_en_6390(void * desc,uint8_t en)762 void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en)
763 {
764 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
765 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
766 }
767
768 static
hal_rx_msdu0_buffer_addr_lsb_6390(void * link_desc_va)769 void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va)
770 {
771 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
772 }
773
774 static
hal_rx_msdu_desc_info_ptr_get_6390(void * msdu0)775 void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0)
776 {
777 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
778 }
779
780 static
hal_ent_mpdu_desc_info_6390(void * ent_ring_desc)781 void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc)
782 {
783 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
784 }
785
786 static
hal_dst_mpdu_desc_info_6390(void * dst_ring_desc)787 void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc)
788 {
789 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
790 }
791
792 static
hal_rx_get_fc_valid_6390(uint8_t * buf)793 uint8_t hal_rx_get_fc_valid_6390(uint8_t *buf)
794 {
795 return HAL_RX_GET_FC_VALID(buf);
796 }
797
hal_rx_get_to_ds_flag_6390(uint8_t * buf)798 static uint8_t hal_rx_get_to_ds_flag_6390(uint8_t *buf)
799 {
800 return HAL_RX_GET_TO_DS_FLAG(buf);
801 }
802
hal_rx_get_mac_addr2_valid_6390(uint8_t * buf)803 static uint8_t hal_rx_get_mac_addr2_valid_6390(uint8_t *buf)
804 {
805 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
806 }
807
hal_rx_get_filter_category_6390(uint8_t * buf)808 static uint8_t hal_rx_get_filter_category_6390(uint8_t *buf)
809 {
810 return HAL_RX_GET_FILTER_CATEGORY(buf);
811 }
812
813 static uint32_t
hal_rx_get_ppdu_id_6390(uint8_t * buf)814 hal_rx_get_ppdu_id_6390(uint8_t *buf)
815 {
816 return HAL_RX_GET_PPDU_ID(buf);
817 }
818
819 /**
820 * hal_reo_config_6390() - Set reo config parameters
821 * @soc: hal soc handle
822 * @reg_val: value to be set
823 * @reo_params: reo parameters
824 *
825 * Return: void
826 */
827 static
hal_reo_config_6390(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)828 void hal_reo_config_6390(struct hal_soc *soc,
829 uint32_t reg_val,
830 struct hal_reo_params *reo_params)
831 {
832 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
833 }
834
835 /**
836 * hal_rx_msdu_desc_info_get_ptr_6390() - Get msdu desc info ptr
837 * @msdu_details_ptr: Pointer to msdu_details_ptr
838 *
839 * Return: Pointer to rx_msdu_desc_info structure.
840 *
841 */
hal_rx_msdu_desc_info_get_ptr_6390(void * msdu_details_ptr)842 static void *hal_rx_msdu_desc_info_get_ptr_6390(void *msdu_details_ptr)
843 {
844 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
845 }
846
847 /**
848 * hal_rx_link_desc_msdu0_ptr_6390() - Get pointer to rx_msdu details
849 * @link_desc: Pointer to link desc
850 *
851 * Return: Pointer to rx_msdu_details structure
852 *
853 */
hal_rx_link_desc_msdu0_ptr_6390(void * link_desc)854 static void *hal_rx_link_desc_msdu0_ptr_6390(void *link_desc)
855 {
856 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
857 }
858
859 /**
860 * hal_rx_msdu_flow_idx_get_6390() - API to get flow index from rx_msdu_end TLV
861 * @buf: pointer to the start of RX PKT TLV headers
862 *
863 * Return: flow index value from MSDU END TLV
864 */
hal_rx_msdu_flow_idx_get_6390(uint8_t * buf)865 static inline uint32_t hal_rx_msdu_flow_idx_get_6390(uint8_t *buf)
866 {
867 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
868 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
869
870 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
871 }
872
873 /**
874 * hal_rx_msdu_flow_idx_invalid_6390() - API to get flow index invalid
875 * from rx_msdu_end TLV
876 * @buf: pointer to the start of RX PKT TLV headers
877 *
878 * Return: flow index invalid value from MSDU END TLV
879 */
hal_rx_msdu_flow_idx_invalid_6390(uint8_t * buf)880 static bool hal_rx_msdu_flow_idx_invalid_6390(uint8_t *buf)
881 {
882 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
883 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
884
885 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
886 }
887
888 /**
889 * hal_rx_msdu_flow_idx_timeout_6390() - API to get flow index timeout
890 * from rx_msdu_end TLV
891 * @buf: pointer to the start of RX PKT TLV headers
892 *
893 * Return: flow index timeout value from MSDU END TLV
894 */
hal_rx_msdu_flow_idx_timeout_6390(uint8_t * buf)895 static bool hal_rx_msdu_flow_idx_timeout_6390(uint8_t *buf)
896 {
897 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
898 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
899
900 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
901 }
902
903 /**
904 * hal_rx_msdu_fse_metadata_get_6390() - API to get FSE metadata
905 * from rx_msdu_end TLV
906 * @buf: pointer to the start of RX PKT TLV headers
907 *
908 * Return: fse metadata value from MSDU END TLV
909 */
hal_rx_msdu_fse_metadata_get_6390(uint8_t * buf)910 static uint32_t hal_rx_msdu_fse_metadata_get_6390(uint8_t *buf)
911 {
912 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
913 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
914
915 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
916 }
917
918 /**
919 * hal_rx_msdu_cce_metadata_get_6390() - API to get CCE metadata
920 * from rx_msdu_end TLV
921 * @buf: pointer to the start of RX PKT TLV headers
922 *
923 * Return: cce metadata
924 */
925 static uint16_t
hal_rx_msdu_cce_metadata_get_6390(uint8_t * buf)926 hal_rx_msdu_cce_metadata_get_6390(uint8_t *buf)
927 {
928 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
929 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
930
931 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
932 }
933
934 /**
935 * hal_rx_msdu_get_flow_params_6390() - API to get flow index, flow index
936 * invalid and flow index timeout from
937 * rx_msdu_end TLV
938 * @buf: pointer to the start of RX PKT TLV headers
939 * @flow_invalid: pointer to return value of flow_idx_valid
940 * @flow_timeout: pointer to return value of flow_idx_timeout
941 * @flow_index: pointer to return value of flow_idx
942 *
943 * Return: none
944 */
945 static inline void
hal_rx_msdu_get_flow_params_6390(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)946 hal_rx_msdu_get_flow_params_6390(uint8_t *buf,
947 bool *flow_invalid,
948 bool *flow_timeout,
949 uint32_t *flow_index)
950 {
951 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
952 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
953
954 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
955 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
956 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
957 }
958
959 /**
960 * hal_rx_tlv_get_tcp_chksum_6390() - API to get tcp checksum
961 * @buf: rx_tlv_hdr
962 *
963 * Return: tcp checksum
964 */
965 static uint16_t
hal_rx_tlv_get_tcp_chksum_6390(uint8_t * buf)966 hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf)
967 {
968 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
969 }
970
971 /**
972 * hal_rx_get_rx_sequence_6390() - Function to retrieve rx sequence number
973 * @buf: Network buffer
974 *
975 * Return: rx sequence number
976 */
977 static
hal_rx_get_rx_sequence_6390(uint8_t * buf)978 uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf)
979 {
980 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
981 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
982
983 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
984 }
985
986 /**
987 * hal_rx_mpdu_start_tlv_tag_valid_6390() - API to check if RX_MPDU_START
988 * tlv tag is valid
989 * @rx_tlv_hdr: start address of rx_pkt_tlvs
990 *
991 * Return: true if RX_MPDU_START is valid, else false.
992 */
hal_rx_mpdu_start_tlv_tag_valid_6390(void * rx_tlv_hdr)993 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6390(void *rx_tlv_hdr)
994 {
995 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
996 uint32_t tlv_tag;
997
998 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
999
1000 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
1001 }
1002
1003 /**
1004 * hal_get_window_address_6390() - Function to get hp/tp address
1005 * @hal_soc: Pointer to hal_soc
1006 * @addr: address offset of register
1007 *
1008 * Return: modified address offset of register
1009 */
hal_get_window_address_6390(struct hal_soc * hal_soc,qdf_iomem_t addr)1010 static inline qdf_iomem_t hal_get_window_address_6390(struct hal_soc *hal_soc,
1011 qdf_iomem_t addr)
1012 {
1013 return addr;
1014 }
1015
1016 /**
1017 * hal_reo_set_err_dst_remap_6390() - Function to set REO error destination
1018 * ring remap register
1019 * @hal_soc: Pointer to hal_soc
1020 *
1021 * Return: none.
1022 */
1023 static void
hal_reo_set_err_dst_remap_6390(void * hal_soc)1024 hal_reo_set_err_dst_remap_6390(void *hal_soc)
1025 {
1026 /*
1027 * Set REO error 2k jump (error code 5) / OOR (error code 7)
1028 * frame routed to REO2TCL ring.
1029 */
1030 uint32_t dst_remap_ix0 =
1031 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 0) |
1032 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 1) |
1033 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 2) |
1034 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 3) |
1035 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 4) |
1036 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
1037 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) |
1038 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7) |
1039 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 8) |
1040 HAL_REO_ERR_REMAP_IX0(REO_REMAP_RELEASE, 9);
1041
1042 HAL_REG_WRITE(hal_soc,
1043 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
1044 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1045 dst_remap_ix0);
1046
1047 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
1048 HAL_REG_READ(
1049 hal_soc,
1050 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
1051 SEQ_WCSS_UMAC_REO_REG_OFFSET)));
1052 }
1053
1054 static
hal_compute_reo_remap_ix2_ix3_6390(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1055 void hal_compute_reo_remap_ix2_ix3_6390(uint32_t *ring, uint32_t num_rings,
1056 uint32_t *remap1, uint32_t *remap2)
1057 {
1058 switch (num_rings) {
1059 case 3:
1060 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1061 HAL_REO_REMAP_IX2(ring[1], 17) |
1062 HAL_REO_REMAP_IX2(ring[2], 18) |
1063 HAL_REO_REMAP_IX2(ring[0], 19) |
1064 HAL_REO_REMAP_IX2(ring[1], 20) |
1065 HAL_REO_REMAP_IX2(ring[2], 21) |
1066 HAL_REO_REMAP_IX2(ring[0], 22) |
1067 HAL_REO_REMAP_IX2(ring[1], 23);
1068
1069 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1070 HAL_REO_REMAP_IX3(ring[0], 25) |
1071 HAL_REO_REMAP_IX3(ring[1], 26) |
1072 HAL_REO_REMAP_IX3(ring[2], 27) |
1073 HAL_REO_REMAP_IX3(ring[0], 28) |
1074 HAL_REO_REMAP_IX3(ring[1], 29) |
1075 HAL_REO_REMAP_IX3(ring[2], 30) |
1076 HAL_REO_REMAP_IX3(ring[0], 31);
1077 break;
1078 case 4:
1079 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1080 HAL_REO_REMAP_IX2(ring[1], 17) |
1081 HAL_REO_REMAP_IX2(ring[2], 18) |
1082 HAL_REO_REMAP_IX2(ring[3], 19) |
1083 HAL_REO_REMAP_IX2(ring[0], 20) |
1084 HAL_REO_REMAP_IX2(ring[1], 21) |
1085 HAL_REO_REMAP_IX2(ring[2], 22) |
1086 HAL_REO_REMAP_IX2(ring[3], 23);
1087
1088 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1089 HAL_REO_REMAP_IX3(ring[1], 25) |
1090 HAL_REO_REMAP_IX3(ring[2], 26) |
1091 HAL_REO_REMAP_IX3(ring[3], 27) |
1092 HAL_REO_REMAP_IX3(ring[0], 28) |
1093 HAL_REO_REMAP_IX3(ring[1], 29) |
1094 HAL_REO_REMAP_IX3(ring[2], 30) |
1095 HAL_REO_REMAP_IX3(ring[3], 31);
1096 break;
1097 }
1098 }
1099
1100 static
hal_compute_reo_remap_ix0_6390(uint32_t * remap0)1101 void hal_compute_reo_remap_ix0_6390(uint32_t *remap0)
1102 {
1103 *remap0 = HAL_REO_REMAP_IX0(REO_REMAP_SW1, 0) |
1104 HAL_REO_REMAP_IX0(REO_REMAP_SW1, 1) |
1105 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 2) |
1106 HAL_REO_REMAP_IX0(REO_REMAP_SW3, 3) |
1107 HAL_REO_REMAP_IX0(REO_REMAP_SW2, 4) |
1108 HAL_REO_REMAP_IX0(REO_REMAP_RELEASE, 5) |
1109 HAL_REO_REMAP_IX0(REO_REMAP_FW, 6) |
1110 HAL_REO_REMAP_IX0(REO_REMAP_FW, 7);
1111 }
1112
1113 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1114 /**
1115 * hal_get_first_wow_wakeup_packet_6390() - Function to get if the buffer is
1116 * the first one that wakes up host
1117 * from WoW.
1118 * @buf: network buffer
1119 *
1120 * Dummy function for QCA6390
1121 *
1122 * Return: 1 to indicate it is first packet received that wakes up host from
1123 * WoW. Otherwise 0
1124 */
hal_get_first_wow_wakeup_packet_6390(uint8_t * buf)1125 static inline uint8_t hal_get_first_wow_wakeup_packet_6390(uint8_t *buf)
1126 {
1127 return 0;
1128 }
1129 #endif
1130
hal_hw_txrx_ops_attach_qca6390(struct hal_soc * hal_soc)1131 static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
1132 {
1133 /* init and setup */
1134 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1135 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1136 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1137 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
1138 hal_soc->ops->hal_get_window_address = hal_get_window_address_6390;
1139 hal_soc->ops->hal_reo_set_err_dst_remap =
1140 hal_reo_set_err_dst_remap_6390;
1141
1142 /* tx */
1143 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1144 hal_tx_desc_set_dscp_tid_table_id_6390;
1145 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390;
1146 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390;
1147 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390;
1148 hal_soc->ops->hal_tx_desc_set_buf_addr =
1149 hal_tx_desc_set_buf_addr_generic_li;
1150 hal_soc->ops->hal_tx_desc_set_search_type =
1151 hal_tx_desc_set_search_type_generic_li;
1152 hal_soc->ops->hal_tx_desc_set_search_index =
1153 hal_tx_desc_set_search_index_generic_li;
1154 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1155 hal_tx_desc_set_cache_set_num_generic_li;
1156 hal_soc->ops->hal_tx_comp_get_status =
1157 hal_tx_comp_get_status_generic_li;
1158 hal_soc->ops->hal_tx_comp_get_release_reason =
1159 hal_tx_comp_get_release_reason_generic_li;
1160 hal_soc->ops->hal_get_wbm_internal_error =
1161 hal_get_wbm_internal_error_generic_li;
1162 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390;
1163 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1164 hal_tx_init_cmd_credit_ring_6390;
1165
1166 /* rx */
1167 hal_soc->ops->hal_rx_msdu_start_nss_get =
1168 hal_rx_msdu_start_nss_get_6390;
1169 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1170 hal_rx_mon_hw_desc_get_mpdu_status_6390;
1171 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6390;
1172 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1173 hal_rx_proc_phyrx_other_receive_info_tlv_6390;
1174
1175 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390;
1176 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1177 hal_rx_dump_rx_attention_tlv_generic_li;
1178 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1179 hal_rx_dump_msdu_start_tlv_6390;
1180 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1181 hal_rx_dump_mpdu_start_tlv_generic_li;
1182 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1183 hal_rx_dump_mpdu_end_tlv_generic_li;
1184 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1185 hal_rx_dump_pkt_hdr_tlv_generic_li;
1186
1187 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6390;
1188 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1189 hal_rx_mpdu_start_tid_get_6390;
1190 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1191 hal_rx_msdu_start_reception_type_get_6390;
1192 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1193 hal_rx_msdu_end_da_idx_get_6390;
1194 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1195 hal_rx_msdu_desc_info_get_ptr_6390;
1196 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1197 hal_rx_link_desc_msdu0_ptr_6390;
1198 hal_soc->ops->hal_reo_status_get_header =
1199 hal_reo_status_get_header_6390;
1200 hal_soc->ops->hal_rx_status_get_tlv_info =
1201 hal_rx_status_get_tlv_info_generic_li;
1202 hal_soc->ops->hal_rx_wbm_err_info_get =
1203 hal_rx_wbm_err_info_get_generic_li;
1204
1205 hal_soc->ops->hal_tx_set_pcp_tid_map =
1206 hal_tx_set_pcp_tid_map_generic_li;
1207 hal_soc->ops->hal_tx_update_pcp_tid_map =
1208 hal_tx_update_pcp_tid_generic_li;
1209 hal_soc->ops->hal_tx_set_tidmap_prty =
1210 hal_tx_update_tidmap_prty_generic_li;
1211 hal_soc->ops->hal_rx_get_rx_fragment_number =
1212 hal_rx_get_rx_fragment_number_6390;
1213 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1214 hal_rx_msdu_end_da_is_mcbc_get_6390;
1215 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1216 hal_rx_msdu_end_sa_is_valid_get_6390;
1217 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1218 hal_rx_msdu_end_sa_idx_get_6390;
1219 hal_soc->ops->hal_rx_desc_is_first_msdu =
1220 hal_rx_desc_is_first_msdu_6390;
1221 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1222 hal_rx_msdu_end_l3_hdr_padding_get_6390;
1223 hal_soc->ops->hal_rx_encryption_info_valid =
1224 hal_rx_encryption_info_valid_6390;
1225 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6390;
1226 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1227 hal_rx_msdu_end_first_msdu_get_6390;
1228 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1229 hal_rx_msdu_end_da_is_valid_get_6390;
1230 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1231 hal_rx_msdu_end_last_msdu_get_6390;
1232 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1233 hal_rx_get_mpdu_mac_ad4_valid_6390;
1234 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1235 hal_rx_mpdu_start_sw_peer_id_get_6390;
1236 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1237 hal_rx_mpdu_peer_meta_data_get_li;
1238 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390;
1239 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390;
1240 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1241 hal_rx_get_mpdu_frame_control_valid_6390;
1242 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1243 hal_rx_get_frame_ctrl_field_li;
1244 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390;
1245 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390;
1246 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390;
1247 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6390;
1248 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1249 hal_rx_get_mpdu_sequence_control_valid_6390;
1250 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6390;
1251 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6390;
1252 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1253 hal_rx_hw_desc_get_ppduid_get_6390;
1254 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1255 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390;
1256 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1257 hal_rx_msdu_end_sa_sw_peer_id_get_6390;
1258 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1259 hal_rx_msdu0_buffer_addr_lsb_6390;
1260 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1261 hal_rx_msdu_desc_info_ptr_get_6390;
1262 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390;
1263 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390;
1264 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390;
1265 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390;
1266 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1267 hal_rx_get_mac_addr2_valid_6390;
1268 hal_soc->ops->hal_rx_get_filter_category =
1269 hal_rx_get_filter_category_6390;
1270 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390;
1271 hal_soc->ops->hal_reo_config = hal_reo_config_6390;
1272 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390;
1273 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1274 hal_rx_msdu_flow_idx_invalid_6390;
1275 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1276 hal_rx_msdu_flow_idx_timeout_6390;
1277 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1278 hal_rx_msdu_fse_metadata_get_6390;
1279 hal_soc->ops->hal_rx_msdu_cce_match_get =
1280 hal_rx_msdu_cce_match_get_li;
1281 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1282 hal_rx_msdu_cce_metadata_get_6390;
1283 hal_soc->ops->hal_rx_msdu_get_flow_params =
1284 hal_rx_msdu_get_flow_params_6390;
1285 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
1286 hal_rx_tlv_get_tcp_chksum_6390;
1287 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390;
1288 /* rx - msdu end fast path info fields */
1289 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1290 hal_rx_msdu_packet_metadata_get_generic_li;
1291 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1292 hal_rx_mpdu_start_tlv_tag_valid_6390;
1293
1294 /* rx - TLV struct offsets */
1295 hal_soc->ops->hal_rx_msdu_end_offset_get =
1296 hal_rx_msdu_end_offset_get_generic;
1297 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
1298 hal_soc->ops->hal_rx_msdu_start_offset_get =
1299 hal_rx_msdu_start_offset_get_generic;
1300 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1301 hal_rx_mpdu_start_offset_get_generic;
1302 hal_soc->ops->hal_rx_mpdu_end_offset_get =
1303 hal_rx_mpdu_end_offset_get_generic;
1304 #ifndef NO_RX_PKT_HDR_TLV
1305 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1306 hal_rx_pkt_tlv_offset_get_generic;
1307 #endif
1308 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1309 hal_compute_reo_remap_ix2_ix3_6390;
1310 hal_soc->ops->hal_setup_link_idle_list =
1311 hal_setup_link_idle_list_generic_li;
1312 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1313 hal_soc->ops->hal_get_first_wow_wakeup_packet =
1314 hal_get_first_wow_wakeup_packet_6390;
1315 #endif
1316 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
1317 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
1318 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1319 hal_rx_tlv_decrypt_err_get_li;
1320 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
1321 hal_rx_tlv_get_pkt_capture_flags_li;
1322 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1323 hal_rx_mpdu_info_ampdu_flag_get_li;
1324 hal_soc->ops->hal_compute_reo_remap_ix0 =
1325 hal_compute_reo_remap_ix0_6390;
1326 };
1327
1328 struct hal_hw_srng_config hw_srng_table_6390[] = {
1329 /* TODO: max_rings can populated by querying HW capabilities */
1330 { /* REO_DST */
1331 .start_ring_id = HAL_SRNG_REO2SW1,
1332 .max_rings = 4,
1333 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1334 .lmac_ring = FALSE,
1335 .ring_dir = HAL_SRNG_DST_RING,
1336 .reg_start = {
1337 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
1338 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1339 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
1340 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1341 },
1342 .reg_size = {
1343 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
1344 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
1345 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
1346 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
1347 },
1348 .max_size =
1349 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
1350 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
1351 },
1352 { /* REO_EXCEPTION */
1353 /* Designating REO2TCL ring as exception ring. This ring is
1354 * similar to other REO2SW rings though it is named as REO2TCL.
1355 * Any of theREO2SW rings can be used as exception ring.
1356 */
1357 .start_ring_id = HAL_SRNG_REO2TCL,
1358 .max_rings = 1,
1359 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1360 .lmac_ring = FALSE,
1361 .ring_dir = HAL_SRNG_DST_RING,
1362 .reg_start = {
1363 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
1364 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1365 HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
1366 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1367 },
1368 /* Single ring - provide ring size if multiple rings of this
1369 * type are supported
1370 */
1371 .reg_size = {},
1372 .max_size =
1373 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
1374 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
1375 },
1376 { /* REO_REINJECT */
1377 .start_ring_id = HAL_SRNG_SW2REO,
1378 .max_rings = 1,
1379 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1380 .lmac_ring = FALSE,
1381 .ring_dir = HAL_SRNG_SRC_RING,
1382 .reg_start = {
1383 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
1384 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1385 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
1386 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1387 },
1388 /* Single ring - provide ring size if multiple rings of this
1389 * type are supported
1390 */
1391 .reg_size = {},
1392 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
1393 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
1394 },
1395 { /* REO_CMD */
1396 .start_ring_id = HAL_SRNG_REO_CMD,
1397 .max_rings = 1,
1398 .entry_size = (sizeof(struct tlv_32_hdr) +
1399 sizeof(struct reo_get_queue_stats)) >> 2,
1400 .lmac_ring = FALSE,
1401 .ring_dir = HAL_SRNG_SRC_RING,
1402 .reg_start = {
1403 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
1404 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1405 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
1406 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1407 },
1408 /* Single ring - provide ring size if multiple rings of this
1409 * type are supported
1410 */
1411 .reg_size = {},
1412 .max_size =
1413 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1414 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1415 },
1416 { /* REO_STATUS */
1417 .start_ring_id = HAL_SRNG_REO_STATUS,
1418 .max_rings = 1,
1419 .entry_size = (sizeof(struct tlv_32_hdr) +
1420 sizeof(struct reo_get_queue_stats_status)) >> 2,
1421 .lmac_ring = FALSE,
1422 .ring_dir = HAL_SRNG_DST_RING,
1423 .reg_start = {
1424 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
1425 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1426 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
1427 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1428 },
1429 /* Single ring - provide ring size if multiple rings of this
1430 * type are supported
1431 */
1432 .reg_size = {},
1433 .max_size =
1434 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1435 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1436 },
1437 { /* TCL_DATA */
1438 .start_ring_id = HAL_SRNG_SW2TCL1,
1439 .max_rings = 3,
1440 .entry_size = (sizeof(struct tlv_32_hdr) +
1441 sizeof(struct tcl_data_cmd)) >> 2,
1442 .lmac_ring = FALSE,
1443 .ring_dir = HAL_SRNG_SRC_RING,
1444 .reg_start = {
1445 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
1446 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1447 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
1448 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1449 },
1450 .reg_size = {
1451 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
1452 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
1453 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
1454 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
1455 },
1456 .max_size =
1457 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
1458 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
1459 },
1460 { /* TCL_CMD */
1461 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
1462 .max_rings = 1,
1463 .entry_size = (sizeof(struct tlv_32_hdr) +
1464 sizeof(struct tcl_gse_cmd)) >> 2,
1465 .lmac_ring = FALSE,
1466 .ring_dir = HAL_SRNG_SRC_RING,
1467 .reg_start = {
1468 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
1469 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1470 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
1471 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1472 },
1473 /* Single ring - provide ring size if multiple rings of this
1474 * type are supported
1475 */
1476 .reg_size = {},
1477 .max_size =
1478 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1479 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1480 },
1481 { /* TCL_STATUS */
1482 .start_ring_id = HAL_SRNG_TCL_STATUS,
1483 .max_rings = 1,
1484 .entry_size = (sizeof(struct tlv_32_hdr) +
1485 sizeof(struct tcl_status_ring)) >> 2,
1486 .lmac_ring = FALSE,
1487 .ring_dir = HAL_SRNG_DST_RING,
1488 .reg_start = {
1489 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
1490 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1491 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
1492 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1493 },
1494 /* Single ring - provide ring size if multiple rings of this
1495 * type are supported
1496 */
1497 .reg_size = {},
1498 .max_size =
1499 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
1500 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
1501 },
1502 { /* CE_SRC */
1503 .start_ring_id = HAL_SRNG_CE_0_SRC,
1504 .max_rings = 12,
1505 .entry_size = sizeof(struct ce_src_desc) >> 2,
1506 .lmac_ring = FALSE,
1507 .ring_dir = HAL_SRNG_SRC_RING,
1508 .reg_start = {
1509 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1510 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
1511 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1512 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
1513 },
1514 .reg_size = {
1515 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
1516 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
1517 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
1518 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
1519 },
1520 .max_size =
1521 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1522 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1523 },
1524 { /* CE_DST */
1525 .start_ring_id = HAL_SRNG_CE_0_DST,
1526 .max_rings = 12,
1527 .entry_size = 8 >> 2,
1528 /*TODO: entry_size above should actually be
1529 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
1530 * of struct ce_dst_desc in HW header files
1531 */
1532 .lmac_ring = FALSE,
1533 .ring_dir = HAL_SRNG_SRC_RING,
1534 .reg_start = {
1535 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1536 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1537 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1538 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1539 },
1540 .reg_size = {
1541 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1542 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1543 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1544 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1545 },
1546 .max_size =
1547 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1548 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1549 },
1550 { /* CE_DST_STATUS */
1551 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
1552 .max_rings = 12,
1553 .entry_size = sizeof(struct ce_stat_desc) >> 2,
1554 .lmac_ring = FALSE,
1555 .ring_dir = HAL_SRNG_DST_RING,
1556 .reg_start = {
1557 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
1558 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1559 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
1560 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1561 },
1562 /* TODO: check destination status ring registers */
1563 .reg_size = {
1564 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1565 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1566 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1567 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1568 },
1569 .max_size =
1570 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1571 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1572 },
1573 { /* WBM_IDLE_LINK */
1574 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
1575 .max_rings = 1,
1576 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
1577 .lmac_ring = FALSE,
1578 .ring_dir = HAL_SRNG_SRC_RING,
1579 .reg_start = {
1580 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1581 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1582 },
1583 /* Single ring - provide ring size if multiple rings of this
1584 * type are supported
1585 */
1586 .reg_size = {},
1587 .max_size =
1588 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
1589 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
1590 },
1591 { /* SW2WBM_RELEASE */
1592 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
1593 .max_rings = 1,
1594 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1595 .lmac_ring = FALSE,
1596 .ring_dir = HAL_SRNG_SRC_RING,
1597 .reg_start = {
1598 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1599 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1600 },
1601 /* Single ring - provide ring size if multiple rings of this
1602 * type are supported
1603 */
1604 .reg_size = {},
1605 .max_size =
1606 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1607 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1608 },
1609 { /* WBM2SW_RELEASE */
1610 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
1611 #ifdef IPA_WDI3_TX_TWO_PIPES
1612 .max_rings = 5,
1613 #else
1614 .max_rings = 4,
1615 #endif
1616 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1617 .lmac_ring = FALSE,
1618 .ring_dir = HAL_SRNG_DST_RING,
1619 .reg_start = {
1620 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1621 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1622 },
1623 .reg_size = {
1624 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
1625 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1626 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
1627 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1628 },
1629 .max_size =
1630 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1631 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1632 },
1633 { /* RXDMA_BUF */
1634 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
1635 #ifdef IPA_OFFLOAD
1636 .max_rings = 3,
1637 #else
1638 .max_rings = 2,
1639 #endif
1640 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1641 .lmac_ring = TRUE,
1642 .ring_dir = HAL_SRNG_SRC_RING,
1643 /* reg_start is not set because LMAC rings are not accessed
1644 * from host
1645 */
1646 .reg_start = {},
1647 .reg_size = {},
1648 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1649 },
1650 { /* RXDMA_DST */
1651 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
1652 .max_rings = 1,
1653 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1654 .lmac_ring = TRUE,
1655 .ring_dir = HAL_SRNG_DST_RING,
1656 /* reg_start is not set because LMAC rings are not accessed
1657 * from host
1658 */
1659 .reg_start = {},
1660 .reg_size = {},
1661 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1662 },
1663 { /* RXDMA_MONITOR_BUF */
1664 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
1665 .max_rings = 1,
1666 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1667 .lmac_ring = TRUE,
1668 .ring_dir = HAL_SRNG_SRC_RING,
1669 /* reg_start is not set because LMAC rings are not accessed
1670 * from host
1671 */
1672 .reg_start = {},
1673 .reg_size = {},
1674 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1675 },
1676 { /* RXDMA_MONITOR_STATUS */
1677 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
1678 .max_rings = 1,
1679 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1680 .lmac_ring = TRUE,
1681 .ring_dir = HAL_SRNG_SRC_RING,
1682 /* reg_start is not set because LMAC rings are not accessed
1683 * from host
1684 */
1685 .reg_start = {},
1686 .reg_size = {},
1687 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1688 },
1689 { /* RXDMA_MONITOR_DST */
1690 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
1691 .max_rings = 1,
1692 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1693 .lmac_ring = TRUE,
1694 .ring_dir = HAL_SRNG_DST_RING,
1695 /* reg_start is not set because LMAC rings are not accessed
1696 * from host
1697 */
1698 .reg_start = {},
1699 .reg_size = {},
1700 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1701 },
1702 { /* RXDMA_MONITOR_DESC */
1703 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
1704 .max_rings = 1,
1705 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1706 .lmac_ring = TRUE,
1707 .ring_dir = HAL_SRNG_SRC_RING,
1708 /* reg_start is not set because LMAC rings are not accessed
1709 * from host
1710 */
1711 .reg_start = {},
1712 .reg_size = {},
1713 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1714 },
1715 { /* DIR_BUF_RX_DMA_SRC */
1716 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
1717 /*
1718 * one ring is for spectral scan
1719 * the other one is for cfr
1720 */
1721 .max_rings = 2,
1722 .entry_size = 2,
1723 .lmac_ring = TRUE,
1724 .ring_dir = HAL_SRNG_SRC_RING,
1725 /* reg_start is not set because LMAC rings are not accessed
1726 * from host
1727 */
1728 .reg_start = {},
1729 .reg_size = {},
1730 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1731 },
1732 #ifdef WLAN_FEATURE_CIF_CFR
1733 { /* WIFI_POS_SRC */
1734 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
1735 .max_rings = 1,
1736 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
1737 .lmac_ring = TRUE,
1738 .ring_dir = HAL_SRNG_SRC_RING,
1739 /* reg_start is not set because LMAC rings are not accessed
1740 * from host
1741 */
1742 .reg_start = {},
1743 .reg_size = {},
1744 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1745 },
1746 #endif
1747 { /* REO2PPE */ 0},
1748 { /* PPE2TCL */ 0},
1749 { /* PPE_RELEASE */ 0},
1750 { /* TX_MONITOR_BUF */ 0},
1751 { /* TX_MONITOR_DST */ 0},
1752 { /* SW2RXDMA_NEW */ 0},
1753 { /* SW2RXDMA_LINK_RELEASE */ 0},
1754 };
1755
1756 /**
1757 * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops,
1758 * offset and srng table
1759 * @hal_soc: HAL SoC context
1760 */
hal_qca6390_attach(struct hal_soc * hal_soc)1761 void hal_qca6390_attach(struct hal_soc *hal_soc)
1762 {
1763 hal_soc->hw_srng_table = hw_srng_table_6390;
1764 hal_srng_hw_reg_offset_init_generic(hal_soc);
1765 hal_hw_txrx_default_ops_attach_li(hal_soc);
1766 hal_hw_txrx_ops_attach_qca6390(hal_soc);
1767 }
1768