1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 /** 19 * DOC: wma_eht.c 20 * 21 * WLAN Host Device Driver 802.11be - Extremely High Throughput Implementation 22 */ 23 24 #include "wma_eht.h" 25 #include "wmi_unified.h" 26 #include "service_ready_param.h" 27 #include "target_if.h" 28 #include "wma_internal.h" 29 30 #if defined(WLAN_FEATURE_11BE) 31 /* MCS Based EHT rate table */ 32 /* MCS parameters with Nss = 1*/ 33 static const struct index_eht_data_rate_type eht_mcs_nss1[] = { 34 /* MCS, {dcm0:0.8/1.6/3.2}, {dcm1:0.8/1.6/3.2} */ 35 {0, {{86, 81, 73}, {0} }, /* EHT20 */ 36 {{172, 163, 146}, {0} }, /* EHT40 */ 37 {{360, 340, 306}, {0} }, /* EHT80 */ 38 {{721, 681, 613}, {0} }, /* EHT160 */ 39 {{1441, 1361, 1225}, {0}}} , /* EHT320 */ 40 {1, {{172, 163, 146 }, {0} }, 41 {{344, 325, 293 }, {0} }, 42 {{721, 681, 613 }, {0} }, 43 {{1441, 1361, 1225}, {0} }, 44 {{2882, 2722, 2450}, {0} } } , 45 {2, {{258, 244, 219 }, {0} }, 46 {{516, 488, 439 }, {0} }, 47 {{1081, 1021, 919 }, {0} }, 48 {{2162, 2042, 1838}, {0} }, 49 {{4324, 4083, 3675}, {0} } } , 50 {3, {{344, 325, 293 }, {0} }, 51 {{688, 650, 585 }, {0} }, 52 {{1441, 1361, 1225}, {0} }, 53 {{2882, 2722, 2450}, {0} }, 54 {{5765, 5444, 4900}, {0} } } , 55 {4, {{516, 488, 439 }, {0} }, 56 {{1032, 975, 878 }, {0} }, 57 {{2162, 2042, 1838}, {0} }, 58 {{4324, 4083, 3675}, {0} }, 59 {{8647, 8167, 7350}, {0} } } , 60 {5, {{688, 650, 585 }, {0} }, 61 {{1376, 1300, 1170}, {0} }, 62 {{2882, 2722, 2450}, {0} }, 63 {{5765, 5444, 4900}, {0} }, 64 {{11529, 10889, 9800}, {0}}} , 65 {6, {{774, 731, 658 }, {0} }, 66 {{1549, 1463, 1316}, {0} }, 67 {{3243, 3063, 2756}, {0} }, 68 {{6485, 6125, 5513}, {0} }, 69 {{12971, 12250, 11025}, {0} } } , 70 {7, {{860, 813, 731 }, {0} }, 71 {{1721, 1625, 1463}, {0} }, 72 {{3603, 3403, 3063}, {0} }, 73 {{7206, 6806, 6125}, {0} }, 74 {{14412, 13611, 12250}, {0} } } , 75 {8, {{1032, 975, 878 }, {0} }, 76 {{2065, 1950, 1755}, {0} }, 77 {{4324, 4083, 3675}, {0} }, 78 {{8647, 8167, 7350}, {0} }, 79 {{17294, 16333, 14700}, {0} }} , 80 {9, {{1147, 1083, 975 }, {0} }, 81 {{2294, 2167, 1950}, {0} }, 82 {{4804, 4537, 4083}, {0} }, 83 {{9608, 9074, 8167}, {0} }, 84 {{19216, 18148, 16333}, {0} } } , 85 {10, {{1290, 1219, 1097}, {0} }, 86 {{2581, 2438, 2194}, {0} }, 87 {{5404, 5104, 4594}, {0} }, 88 {{10809, 10208, 9188}, {0} }, 89 {{21618, 20417, 18375}, {0} } } , 90 {11, {{1434, 1354, 1219}, {0} }, 91 {{2868, 2708, 2438}, {0} }, 92 {{6005, 5671, 5104}, {0} }, 93 {{12010, 11342, 10208}, {0} }, 94 {{24020, 22685, 20417}, {0} }} , 95 {12, {{1549, 1463, 1316}, {0} }, 96 {{3097, 2925, 2633}, {0} }, 97 {{6485, 6125, 5513}, {0} }, 98 {{12971, 12250, 11025}, {0} }, 99 {{25941, 24500, 22050}, {0} }} , 100 {13, {{1721, 1625, 1463}, {0} }, 101 {{3441, 3250, 2925}, {0} }, 102 {{7206, 6806, 6125}, {0} }, 103 {{14412, 13611, 12250}, {0}}, 104 {{28824, 27222, 24500}, {0}}} , 105 }; 106 107 /*MCS parameters with Nss = 2*/ 108 static const struct index_eht_data_rate_type eht_mcs_nss2[] = { 109 /* MCS, {dcm0:0.8/1.6/3.2}, {dcm1:0.8/1.6/3.2} */ 110 {0, {{172, 162, 146 }, {0} }, /* EHT20 */ 111 {{344, 326, 292 }, {0} }, /* EHT40 */ 112 {{720, 680, 612 }, {0} }, /* EHT80 */ 113 {{1442, 1362, 1226}, {0} }, /* EHT160 */ 114 {{2882, 2722, 2450}, {0} } } , /* EHT320 */ 115 {1, {{344, 326, 292 }, {0} }, 116 {{688, 650, 586 }, {0} }, 117 {{1442, 1362, 1226}, {0} }, 118 {{2882, 2722, 2450}, {0}}, 119 {{5764, 5444, 4900}, {0} }} , 120 {2, {{516, 488, 438 }, {0} }, 121 {{1032, 976, 878 }, {0} }, 122 {{2162, 2042, 1838}, {0} }, 123 {{4324, 4084, 3676}, {0} }, 124 {{8648, 8166, 7350}, {0} } } , 125 {3, {{688, 650, 586 }, {0} }, 126 {{1376, 1300, 1170}, {0} }, 127 {{2882, 2722, 2450}, {0} }, 128 {{5764, 5444, 4900}, {0} }, 129 {{11530, 10888, 9800}, {0}} } , 130 {4, {{1032, 976, 878 }, {0} }, 131 {{2064, 1950, 1756}, {0} }, 132 {{4324, 4083, 36756}, {0} }, 133 {{8648, 8166, 7350}, {0} }, 134 {{17294, 16334, 14700}, {0}}}, 135 {5, {{1376, 1300, 1170}, {0} }, 136 {{2752, 2600, 2340}, {0} }, 137 {{5764, 5444, 4900}, {0} }, 138 {{11530, 10888, 9800}, {0} }, 139 {{23058, 21778, 19600}, {0} }} , 140 {6, {{1548, 1462, 1316}, {0} }, 141 {{3098, 2926, 2632}, {0} }, 142 {{6486, 6126, 5512}, {0} }, 143 {{12970, 12250, 11026}, {0} }, 144 {{25942, 24500, 22050}, {0} }} , 145 {7, {{1720, 1626, 1462}, {0} }, 146 {{3442, 3250, 2926}, {0} }, 147 {{7206, 6806, 61256}, {0} }, 148 {{14412, 13612, 12250}, {0} }, 149 {{28824, 27222, 24500}, {0} }} , 150 {8, {{2064, 1950, 1756}, {0} }, 151 {{4130, 3900, 3510}, {0} }, 152 {{8648, 8166, 7350}, {0} }, 153 {{17294, 16334, 14700}, {0} }, 154 {{34588, 32666, 29400}, {0} }} , 155 {9, {{2294, 2166, 1950}, {0} }, 156 {{4588, 4334, 3900}, {0} }, 157 {{9608, 9074, 8166}, {0} }, 158 {{19216, 18148, 16334}, {0} }, 159 {{38432, 36296, 32666}, {0} }} , 160 {10, {{2580, 2438, 2194}, {0} }, 161 {{5162, 4876, 4388}, {0} }, 162 {{10808, 10208, 9188}, {0} }, 163 {{21618, 20416, 18376}, {0} }, 164 {{43236, 40834, 36750}, {0} }} , 165 {11, {{2868, 2708, 2438}, {0} }, 166 {{5736, 5416, 4876}, {0} }, 167 {{12010, 11342, 10208}, {0} }, 168 {{24020, 22686, 20416}, {0} }, 169 {{48040, 45370, 40834}, {0} }} , 170 {12, {{3098, 2926, 2632}, {0} }, 171 {{6194, 5850, 5266}, {0} }, 172 {{12970, 12250, 11026}, {0} }, 173 {{25942, 24500, 22050}, {0} }, 174 {{51882, 49000, 44100}, {0} }} , 175 {13, {{3442, 3250, 2926}, {0} }, 176 {{6882, 6500, 5850}, {0} }, 177 {{14412, 13611, 12250}, {0} }, 178 {{28824, 27222, 24500}, {0} }, 179 {{57648, 54444, 49000}, {0} }} 180 }; 181 182 /** 183 * wma_convert_eht_cap() - convert EHT capabilities into dot11f structure 184 * @eht_cap: pointer to dot11f structure 185 * @mac_cap: Received EHT MAC capability 186 * @phy_cap: Received EHT PHY capability 187 * 188 * This function converts various EHT capability received as part of extended 189 * service ready event into dot11f structure. 190 * 191 * Return: None 192 */ 193 static void wma_convert_eht_cap(tDot11fIEeht_cap *eht_cap, uint32_t *mac_cap, 194 uint32_t *phy_cap) 195 { 196 eht_cap->present = true; 197 198 /* EHT MAC capabilities */ 199 eht_cap->epcs_pri_access = WMI_EHTCAP_MAC_NSEPPRIACCESS_GET(mac_cap); 200 eht_cap->eht_om_ctl = WMI_EHTCAP_MAC_EHTOMCTRL_GET(mac_cap); 201 eht_cap->triggered_txop_sharing_mode1 = 202 WMI_EHTCAP_MAC_TRIGTXOPMODE1_GET(mac_cap); 203 eht_cap->triggered_txop_sharing_mode2 = 204 WMI_EHTCAP_MAC_TRIGTXOPMODE2_GET(mac_cap); 205 eht_cap->restricted_twt = WMI_EHTCAP_MAC_RESTRICTTWT_GET(mac_cap); 206 eht_cap->scs_traffic_desc = WMI_EHTCAP_MAC_SCSTRAFFICDESC_GET(mac_cap); 207 eht_cap->max_mpdu_len = WMI_EHTCAP_MAC_MAXMPDULEN_GET(mac_cap); 208 eht_cap->max_a_mpdu_len_exponent_ext = 209 WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_GET(mac_cap); 210 eht_cap->eht_trs_support = 211 WMI_EHTCAP_MAC_TRS_SUPPORT_GET(mac_cap); 212 eht_cap->txop_return_support_txop_share_m2 = 213 WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_GET(mac_cap); 214 215 /* EHT PHY capabilities */ 216 eht_cap->support_320mhz_6ghz = WMI_EHTCAP_PHY_320MHZIN6GHZ_GET(phy_cap); 217 eht_cap->ru_242tone_wt_20mhz = WMI_EHTCAP_PHY_242TONERUBWLT20MHZ_GET( 218 phy_cap); 219 eht_cap->ndp_4x_eht_ltf_3dot2_us_gi = 220 WMI_EHTCAP_PHY_NDP4XEHTLTFAND320NSGI_GET(phy_cap); 221 eht_cap->partial_bw_mu_mimo = WMI_EHTCAP_PHY_PARTIALBWULMU_GET(phy_cap); 222 eht_cap->su_beamformer = WMI_EHTCAP_PHY_SUBFMR_GET(phy_cap); 223 eht_cap->su_beamformee = WMI_EHTCAP_PHY_SUBFME_GET(phy_cap); 224 eht_cap->bfee_ss_le_80mhz = WMI_EHTCAP_PHY_BFMESSLT80MHZ_GET(phy_cap); 225 eht_cap->bfee_ss_160mhz = WMI_EHTCAP_PHY_BFMESS160MHZ_GET(phy_cap); 226 eht_cap->bfee_ss_320mhz = WMI_EHTCAP_PHY_BFMESS320MHZ_GET(phy_cap); 227 eht_cap->num_sounding_dim_le_80mhz = WMI_EHTCAP_PHY_NUMSOUNDLT80MHZ_GET( 228 phy_cap); 229 eht_cap->num_sounding_dim_160mhz = WMI_EHTCAP_PHY_NUMSOUND160MHZ_GET( 230 phy_cap); 231 eht_cap->num_sounding_dim_320mhz = WMI_EHTCAP_PHY_NUMSOUND320MHZ_GET( 232 phy_cap); 233 eht_cap->ng_16_su_feedback = WMI_EHTCAP_PHY_NG16SUFB_GET(phy_cap); 234 eht_cap->ng_16_mu_feedback = WMI_EHTCAP_PHY_NG16MUFB_GET(phy_cap); 235 eht_cap->cb_sz_4_2_su_feedback = WMI_EHTCAP_PHY_CODBK42SUFB_GET( 236 phy_cap); 237 eht_cap->cb_sz_7_5_su_feedback = WMI_EHTCAP_PHY_CODBK75MUFB_GET( 238 phy_cap); 239 eht_cap->trig_su_bforming_feedback = WMI_EHTCAP_PHY_TRIGSUBFFB_GET( 240 phy_cap); 241 eht_cap->trig_mu_bforming_partial_bw_feedback = 242 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_GET(phy_cap); 243 eht_cap->triggered_cqi_feedback = WMI_EHTCAP_PHY_TRIGCQIFB_GET(phy_cap); 244 eht_cap->partial_bw_dl_mu_mimo = WMI_EHTCAP_PHY_PARTBWDLMUMIMO_GET( 245 phy_cap); 246 eht_cap->psr_based_sr = WMI_EHTCAP_PHY_PSRSR_GET(phy_cap); 247 eht_cap->power_boost_factor = WMI_EHTCAP_PHY_PWRBSTFACTOR_GET(phy_cap); 248 eht_cap->eht_mu_ppdu_4x_ltf_0_8_us_gi = 249 WMI_EHTCAP_PHY_4XEHTLTFAND800NSGI_GET(phy_cap); 250 eht_cap->max_nc = WMI_EHTCAP_PHY_MAXNC_GET(phy_cap); 251 eht_cap->non_trig_cqi_feedback = WMI_EHTCAP_PHY_NONTRIGCQIFB_GET( 252 phy_cap); 253 eht_cap->tx_1024_4096_qam_lt_242_tone_ru = 254 WMI_EHTCAP_PHY_TX1024AND4096QAMLS242TONERU_GET(phy_cap); 255 eht_cap->rx_1024_4096_qam_lt_242_tone_ru = 256 WMI_EHTCAP_PHY_RX1024AND4096QAMLS242TONERU_GET(phy_cap); 257 eht_cap->ppet_present = WMI_EHTCAP_PHY_PPETHRESPRESENT_GET(phy_cap); 258 eht_cap->common_nominal_pkt_padding = WMI_EHTCAP_PHY_CMNNOMPKTPAD_GET( 259 phy_cap); 260 eht_cap->max_num_eht_ltf = WMI_EHTCAP_PHY_MAXNUMEHTLTF_GET(phy_cap); 261 eht_cap->mcs_15 = WMI_EHTCAP_PHY_SUPMCS15_GET(phy_cap); 262 eht_cap->eht_dup_6ghz = WMI_EHTCAP_PHY_EHTDUPIN6GHZ_GET(phy_cap); 263 eht_cap->op_sta_rx_ndp_wider_bw_20mhz = 264 WMI_EHTCAP_PHY_20MHZOPSTARXNDPWIDERBW_GET(phy_cap); 265 eht_cap->non_ofdma_ul_mu_mimo_le_80mhz = 266 WMI_EHTCAP_PHY_NONOFDMAULMUMIMOLT80MHZ_GET(phy_cap); 267 eht_cap->non_ofdma_ul_mu_mimo_160mhz = 268 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO160MHZ_GET(phy_cap); 269 eht_cap->non_ofdma_ul_mu_mimo_320mhz = 270 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO320MHZ_GET(phy_cap); 271 eht_cap->mu_bformer_le_80mhz = WMI_EHTCAP_PHY_MUBFMRLT80MHZ_GET( 272 phy_cap); 273 eht_cap->mu_bformer_160mhz = WMI_EHTCAP_PHY_MUBFMR160MHZ_GET(phy_cap); 274 eht_cap->mu_bformer_320mhz = WMI_EHTCAP_PHY_MUBFMR320MHZ_GET(phy_cap); 275 eht_cap->tb_sounding_feedback_rl = 276 WMI_EHTCAP_PHY_TBSUNDFBRATELIMIT_GET(phy_cap); 277 eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma = 278 WMI_EHTCAP_PHY_RX1024QAMWIDERBWDLOFDMA_GET(phy_cap); 279 eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma = 280 WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(phy_cap); 281 282 /* TODO: MCS map and PPET */ 283 } 284 285 void wma_eht_update_tgt_services(struct wmi_unified *wmi_handle, 286 struct wma_tgt_services *cfg) 287 { 288 if (wmi_service_enabled(wmi_handle, wmi_service_11be)) { 289 cfg->en_11be = true; 290 wma_set_fw_wlan_feat_caps(DOT11BE); 291 wma_debug("11be is enabled"); 292 } else { 293 cfg->en_11be = false; 294 wma_debug("11be is not enabled"); 295 } 296 } 297 298 static void 299 wma_update_eht_cap_support_for_320mhz(struct target_psoc_info *tgt_hdl, 300 tDot11fIEeht_cap *eht_cap) 301 { 302 struct wlan_psoc_host_mac_phy_caps_ext2 *cap; 303 304 cap = target_psoc_get_mac_phy_cap_ext2_for_mode( 305 tgt_hdl, WMI_HOST_HW_MODE_SINGLE); 306 if (!cap) { 307 wma_debug("HW_MODE_SINGLE does not exist"); 308 return; 309 } 310 311 eht_cap->support_320mhz_6ghz = WMI_EHTCAP_PHY_320MHZIN6GHZ_GET( 312 cap->eht_cap_phy_info_5G); 313 eht_cap->max_num_eht_ltf = 314 WMI_EHTCAP_PHY_MAXNUMEHTLTF_GET(cap->eht_cap_phy_info_5G); 315 wma_debug("Support for 320MHz 0x%01x, max_num_eht_ltf %d", 316 eht_cap->support_320mhz_6ghz, eht_cap->max_num_eht_ltf); 317 } 318 319 static void 320 wma_update_eht_20mhz_only_mcs(uint32_t *mcs_2g_20, tDot11fIEeht_cap *eht_cap) 321 { 322 eht_cap->bw_20_rx_max_nss_for_mcs_0_to_7 |= QDF_GET_BITS(*mcs_2g_20, 0, 4); 323 eht_cap->bw_20_tx_max_nss_for_mcs_0_to_7 |= QDF_GET_BITS(*mcs_2g_20, 4, 4); 324 eht_cap->bw_20_rx_max_nss_for_mcs_8_and_9 |= QDF_GET_BITS(*mcs_2g_20, 8, 4); 325 eht_cap->bw_20_tx_max_nss_for_mcs_8_and_9 |= 326 QDF_GET_BITS(*mcs_2g_20, 12, 4); 327 eht_cap->bw_20_rx_max_nss_for_mcs_10_and_11 |= 328 QDF_GET_BITS(*mcs_2g_20, 16, 4); 329 eht_cap->bw_20_tx_max_nss_for_mcs_10_and_11 |= 330 QDF_GET_BITS(*mcs_2g_20, 20, 4); 331 eht_cap->bw_20_rx_max_nss_for_mcs_12_and_13 |= 332 QDF_GET_BITS(*mcs_2g_20, 24, 4); 333 eht_cap->bw_20_tx_max_nss_for_mcs_12_and_13 |= 334 QDF_GET_BITS(*mcs_2g_20, 28, 4); 335 } 336 337 static void 338 wma_update_eht_le_80mhz_mcs(uint32_t *mcs_le_80, tDot11fIEeht_cap *eht_cap) 339 { 340 eht_cap->bw_le_80_rx_max_nss_for_mcs_0_to_9 |= 341 QDF_GET_BITS(*mcs_le_80, 0, 4); 342 eht_cap->bw_le_80_tx_max_nss_for_mcs_0_to_9 |= 343 QDF_GET_BITS(*mcs_le_80, 4, 4); 344 eht_cap->bw_le_80_rx_max_nss_for_mcs_10_and_11 |= 345 QDF_GET_BITS(*mcs_le_80, 8, 4); 346 eht_cap->bw_le_80_tx_max_nss_for_mcs_10_and_11 |= 347 QDF_GET_BITS(*mcs_le_80, 12, 4); 348 eht_cap->bw_le_80_rx_max_nss_for_mcs_12_and_13 |= 349 QDF_GET_BITS(*mcs_le_80, 16, 4); 350 eht_cap->bw_le_80_tx_max_nss_for_mcs_12_and_13 |= 351 QDF_GET_BITS(*mcs_le_80, 20, 4); 352 } 353 354 static void 355 wma_update_eht_160mhz_mcs(uint32_t *mcs_160mhz, tDot11fIEeht_cap *eht_cap) 356 { 357 eht_cap->bw_160_rx_max_nss_for_mcs_0_to_9 |= 358 QDF_GET_BITS(*mcs_160mhz, 0, 4); 359 eht_cap->bw_160_tx_max_nss_for_mcs_0_to_9 |= 360 QDF_GET_BITS(*mcs_160mhz, 4, 4); 361 eht_cap->bw_160_rx_max_nss_for_mcs_10_and_11 |= 362 QDF_GET_BITS(*mcs_160mhz, 8, 4); 363 eht_cap->bw_160_tx_max_nss_for_mcs_10_and_11 |= 364 QDF_GET_BITS(*mcs_160mhz, 12, 4); 365 eht_cap->bw_160_rx_max_nss_for_mcs_12_and_13 |= 366 QDF_GET_BITS(*mcs_160mhz, 16, 4); 367 eht_cap->bw_160_tx_max_nss_for_mcs_12_and_13 |= 368 QDF_GET_BITS(*mcs_160mhz, 20, 4); 369 } 370 371 static void 372 wma_update_eht_320mhz_mcs(uint32_t *mcs_320mhz, tDot11fIEeht_cap *eht_cap) 373 { 374 eht_cap->bw_320_rx_max_nss_for_mcs_0_to_9 |= 375 QDF_GET_BITS(*mcs_320mhz, 0, 4); 376 eht_cap->bw_320_tx_max_nss_for_mcs_0_to_9 |= 377 QDF_GET_BITS(*mcs_320mhz, 4, 4); 378 eht_cap->bw_320_rx_max_nss_for_mcs_10_and_11 |= 379 QDF_GET_BITS(*mcs_320mhz, 8, 4); 380 eht_cap->bw_320_tx_max_nss_for_mcs_10_and_11 |= 381 QDF_GET_BITS(*mcs_320mhz, 12, 4); 382 eht_cap->bw_320_rx_max_nss_for_mcs_12_and_13 |= 383 QDF_GET_BITS(*mcs_320mhz, 16, 4); 384 eht_cap->bw_320_tx_max_nss_for_mcs_12_and_13 |= 385 QDF_GET_BITS(*mcs_320mhz, 20, 4); 386 } 387 388 void wma_update_target_ext_eht_cap(struct target_psoc_info *tgt_hdl, 389 struct wma_tgt_cfg *tgt_cfg) 390 { 391 tDot11fIEeht_cap *eht_cap = &tgt_cfg->eht_cap; 392 tDot11fIEeht_cap *eht_cap_2g = &tgt_cfg->eht_cap_2g; 393 tDot11fIEeht_cap *eht_cap_5g = &tgt_cfg->eht_cap_5g; 394 int i, num_hw_modes, total_mac_phy_cnt; 395 tDot11fIEeht_cap eht_cap_mac; 396 struct wlan_psoc_host_mac_phy_caps_ext2 *mac_phy_cap, *mac_phy_caps2; 397 struct wlan_psoc_host_mac_phy_caps *host_cap; 398 uint32_t supported_bands; 399 uint32_t *mcs_supp; 400 401 qdf_mem_zero(eht_cap_2g, sizeof(tDot11fIEeht_cap)); 402 qdf_mem_zero(eht_cap_5g, sizeof(tDot11fIEeht_cap)); 403 num_hw_modes = target_psoc_get_num_hw_modes(tgt_hdl); 404 mac_phy_cap = target_psoc_get_mac_phy_cap_ext2(tgt_hdl); 405 host_cap = target_psoc_get_mac_phy_cap(tgt_hdl); 406 total_mac_phy_cnt = target_psoc_get_total_mac_phy_cnt(tgt_hdl); 407 if (!mac_phy_cap || !host_cap) { 408 wma_err("Invalid MAC PHY capabilities handle"); 409 eht_cap->present = false; 410 return; 411 } 412 413 if (!num_hw_modes) { 414 wma_err("No extended EHT cap for current SOC"); 415 eht_cap->present = false; 416 return; 417 } 418 419 if (!tgt_cfg->services.en_11be) { 420 wma_info("Target does not support 11BE"); 421 eht_cap->present = false; 422 return; 423 } 424 425 for (i = 0; i < total_mac_phy_cnt; i++) { 426 supported_bands = host_cap[i].supported_bands; 427 qdf_mem_zero(&eht_cap_mac, sizeof(tDot11fIEeht_cap)); 428 mac_phy_caps2 = &mac_phy_cap[i]; 429 if (supported_bands & WLAN_2G_CAPABILITY) { 430 wma_convert_eht_cap(&eht_cap_mac, 431 mac_phy_caps2->eht_cap_info_2G, 432 mac_phy_caps2->eht_cap_phy_info_2G); 433 /* TODO: PPET */ 434 /* WMI_EHT_SUPP_MCS_20MHZ_ONLY */ 435 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_2G[0]; 436 wma_update_eht_20mhz_only_mcs(mcs_supp, &eht_cap_mac); 437 /* WMI_EHT_SUPP_MCS_LE_80MHZ */ 438 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_2G[1]; 439 wma_update_eht_le_80mhz_mcs(mcs_supp, &eht_cap_mac); 440 441 qdf_mem_copy(eht_cap_2g, &eht_cap_mac, 442 sizeof(tDot11fIEeht_cap)); 443 } 444 445 if (supported_bands & WLAN_5G_CAPABILITY) { 446 qdf_mem_zero(&eht_cap_mac, sizeof(tDot11fIEeht_cap)); 447 wma_convert_eht_cap(&eht_cap_mac, 448 mac_phy_caps2->eht_cap_info_5G, 449 mac_phy_caps2->eht_cap_phy_info_5G); 450 451 /* WMI_EHT_SUPP_MCS_20MHZ_ONLY */ 452 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[0]; 453 wma_update_eht_20mhz_only_mcs(mcs_supp, &eht_cap_mac); 454 /* WMI_EHT_SUPP_MCS_LE_80MHZ */ 455 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[1]; 456 wma_update_eht_le_80mhz_mcs(mcs_supp, &eht_cap_mac); 457 458 /* WMI_EHT_SUPP_MCS_160MHZ */ 459 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[2]; 460 wma_update_eht_160mhz_mcs(mcs_supp, &eht_cap_mac); 461 /* WMI_EHT_SUPP_MCS_320MHZ */ 462 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[3]; 463 wma_update_eht_320mhz_mcs(mcs_supp, &eht_cap_mac); 464 465 qdf_mem_copy(eht_cap_5g, &eht_cap_mac, 466 sizeof(tDot11fIEeht_cap)); 467 } 468 } 469 qdf_mem_copy(eht_cap, &eht_cap_mac, sizeof(tDot11fIEeht_cap)); 470 471 wma_update_eht_cap_support_for_320mhz(tgt_hdl, eht_cap); 472 wma_update_eht_cap_support_for_320mhz(tgt_hdl, eht_cap_5g); 473 474 wma_print_eht_cap(eht_cap); 475 } 476 477 void wma_update_vdev_eht_ops(uint32_t *eht_ops, tDot11fIEeht_op *eht_op) 478 { 479 } 480 481 void wma_print_eht_cap(tDot11fIEeht_cap *eht_cap) 482 { 483 if (!eht_cap->present) 484 return; 485 486 wma_debug("EHT Capabilities:"); 487 488 /* EHT MAC Capabilities */ 489 wma_nofl_debug("\tEPCS Priority Access: 0x%01x", 490 eht_cap->epcs_pri_access); 491 wma_nofl_debug("\tOM Control: 0x%01x", eht_cap->eht_om_ctl); 492 wma_nofl_debug("\tTriggered TXOP Sharing mode-1: 0x%01x", 493 eht_cap->triggered_txop_sharing_mode1); 494 wma_nofl_debug("\tTriggered TXOP Sharing mode-2: 0x%01x", 495 eht_cap->triggered_txop_sharing_mode2); 496 wma_nofl_debug("\tRestricted TWT support: 0x%01x", 497 eht_cap->restricted_twt); 498 wma_nofl_debug("\tSCS Traffic Description Support: 0x%01x", 499 eht_cap->scs_traffic_desc); 500 wma_nofl_debug("\tMaximum MPDU Length: 0x%01x", 501 eht_cap->max_mpdu_len); 502 wma_nofl_debug("\tMaximum A-MPDU Length Exponent Extension: 0x%01x", 503 eht_cap->max_a_mpdu_len_exponent_ext); 504 wma_nofl_debug("\tEHT TRS SUPPORT: 0x%01x", 505 eht_cap->eht_trs_support); 506 wma_nofl_debug("\tTXOP Return Support in TXOP Sharing Mode 2: 0x%01x", 507 eht_cap->txop_return_support_txop_share_m2); 508 509 /* EHT PHY Capabilities */ 510 wma_nofl_debug("\t320 MHz In 6 GHz: 0x%01x", 511 eht_cap->support_320mhz_6ghz); 512 wma_nofl_debug("\t242-tone RU In BW Wider Than 20 MHz: 0x%01x", 513 eht_cap->ru_242tone_wt_20mhz); 514 wma_nofl_debug("\tNDP With 4x EHT-LTF And 3.2 us GI: 0x%01x", 515 eht_cap->ndp_4x_eht_ltf_3dot2_us_gi); 516 wma_nofl_debug("\tPartial Bandwidth UL MU-MIMO: 0x%01x", 517 eht_cap->partial_bw_mu_mimo); 518 wma_nofl_debug("\tSU Beamformer: 0x%01x", eht_cap->su_beamformer); 519 wma_nofl_debug("\tSU Beamformee: 0x%01x", eht_cap->su_beamformee); 520 wma_nofl_debug("\tBeamformee SS <= 80 MHz: 0x%03x", 521 eht_cap->bfee_ss_le_80mhz); 522 wma_nofl_debug("\tBeamformee SS = 160 MHz: 0x%03x", 523 eht_cap->bfee_ss_160mhz); 524 wma_nofl_debug("\tBeamformee SS = 320 MHz: 0x%03x", 525 eht_cap->bfee_ss_320mhz); 526 wma_nofl_debug("\tNumber Of Sounding Dimensions <= 80 MHz: 0x%03x", 527 eht_cap->num_sounding_dim_le_80mhz); 528 wma_nofl_debug("\tNumber Of Sounding Dimensions = 160 MHz: 0x%03x", 529 eht_cap->num_sounding_dim_160mhz); 530 wma_nofl_debug("\tNumber Of Sounding Dimensions = 320 MHz: 0x%03x", 531 eht_cap->num_sounding_dim_320mhz); 532 wma_nofl_debug("\tNg = 16 SU Feedback: 0x%01x", 533 eht_cap->ng_16_su_feedback); 534 wma_nofl_debug("\tNg = 16 MU Feedback: 0x%01x", 535 eht_cap->ng_16_mu_feedback); 536 wma_nofl_debug("\tCodebook Size 4 2 SU Feedback: 0x%01x", 537 eht_cap->cb_sz_4_2_su_feedback); 538 wma_nofl_debug("\tCodebook Size 7 5 MU Feedback: 0x%01x", 539 eht_cap->cb_sz_7_5_su_feedback); 540 wma_nofl_debug("\tTriggered SU Beamforming Feedback: 0x%01x", 541 eht_cap->trig_su_bforming_feedback); 542 wma_nofl_debug("\tTriggered MU Beamforming Partial BW Feedback: 0x%01x", 543 eht_cap->trig_mu_bforming_partial_bw_feedback); 544 wma_nofl_debug("\tTriggered CQI Feedback: 0x%01x", 545 eht_cap->triggered_cqi_feedback); 546 wma_nofl_debug("\tPartial Bandwidth DL MU-MIMO: 0x%01x", 547 eht_cap->partial_bw_dl_mu_mimo); 548 wma_nofl_debug("\tPSR-Based SR: 0x%01x", eht_cap->psr_based_sr); 549 wma_nofl_debug("\tPower Boost Factor: 0x%01x", 550 eht_cap->power_boost_factor); 551 wma_nofl_debug("\tMU PPDU With 4x EHT-LTF 0.8 us GI: 0x%01x", 552 eht_cap->eht_mu_ppdu_4x_ltf_0_8_us_gi); 553 wma_nofl_debug("\tMax Nc: 0x%04x", eht_cap->max_nc); 554 wma_nofl_debug("\tNon-Triggered CQI Feedback: 0x%01x", 555 eht_cap->non_trig_cqi_feedback); 556 wma_nofl_debug("\tTx 1024-QAM 4096-QAM < 242-tone RU: 0x%01x", 557 eht_cap->tx_1024_4096_qam_lt_242_tone_ru); 558 wma_nofl_debug("\tRx 1024-QAM 4096-QAM < 242-tone RU: 0x%01x", 559 eht_cap->rx_1024_4096_qam_lt_242_tone_ru); 560 wma_nofl_debug("\tPPE Thresholds Present: 0x%01x", 561 eht_cap->ppet_present); 562 wma_nofl_debug("\tCommon Nominal Packet Padding: 0x%02x", 563 eht_cap->common_nominal_pkt_padding); 564 wma_nofl_debug("\tMaximum Number Of Supported EHT-LTFs: 0x%05x", 565 eht_cap->max_num_eht_ltf); 566 wma_nofl_debug("\tSupport of MCS 15: 0x%04x", eht_cap->mcs_15); 567 wma_nofl_debug("\tSupport Of EHT DUP In 6 GHz: 0x%01x", 568 eht_cap->eht_dup_6ghz); 569 wma_nofl_debug("\t20 MHz STA RX NDP With Wider BW: 0x%01x", 570 eht_cap->op_sta_rx_ndp_wider_bw_20mhz); 571 wma_nofl_debug("\tNon-OFDMA UL MU-MIMO BW <= 80 MHz: 0x%01x", 572 eht_cap->non_ofdma_ul_mu_mimo_le_80mhz); 573 wma_nofl_debug("\tNon-OFDMA UL MU-MIMO BW = 160 MHz: 0x%01x", 574 eht_cap->non_ofdma_ul_mu_mimo_160mhz); 575 wma_nofl_debug("\tNon-OFDMA UL MU-MIMO BW = 320 MHz: 0x%01x", 576 eht_cap->non_ofdma_ul_mu_mimo_320mhz); 577 wma_nofl_debug("\tMU Beamformer BW <= 80 MHz: 0x%01x", 578 eht_cap->mu_bformer_le_80mhz); 579 wma_nofl_debug("\tMU Beamformer BW = 160 MHz: 0x%01x", 580 eht_cap->mu_bformer_160mhz); 581 wma_nofl_debug("\tMU Beamformer BW = 320 MHz: 0x%01x", 582 eht_cap->mu_bformer_320mhz); 583 wma_nofl_debug("\tTB sounding feedback rate limit: 0x%01x", 584 eht_cap->tb_sounding_feedback_rl); 585 wma_nofl_debug("\tRx 1024-QAM in wider bandwidth DL OFDMA support: 0x%01x", 586 eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma); 587 wma_nofl_debug("\tRx 4096-QAM in wider bandwidth DL OFDMA support: 0x%01x", 588 eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma); 589 wma_nofl_debug("\t EHT MCS 20 rx 0-7 0x%x", 590 eht_cap->bw_20_rx_max_nss_for_mcs_0_to_7); 591 wma_nofl_debug("\t EHT MCS 20 tx 0-7 0x%x", 592 eht_cap->bw_20_tx_max_nss_for_mcs_0_to_7); 593 wma_nofl_debug("\t EHT MCS 20 rx 8-9 0x%x", 594 eht_cap->bw_20_rx_max_nss_for_mcs_8_and_9); 595 wma_nofl_debug("\t EHT MCS 20 tx 8-9 0x%x", 596 eht_cap->bw_20_tx_max_nss_for_mcs_8_and_9); 597 wma_nofl_debug("\t EHT MCS 20 rx 10-11 0x%x", 598 eht_cap->bw_20_rx_max_nss_for_mcs_10_and_11); 599 wma_nofl_debug("\t EHT MCS 20 tx 10-11 0x%x", 600 eht_cap->bw_20_tx_max_nss_for_mcs_10_and_11); 601 wma_nofl_debug("\t EHT MCS 20 rx 12-13 0x%x", 602 eht_cap->bw_20_rx_max_nss_for_mcs_12_and_13); 603 wma_nofl_debug("\t EHT MCS 20 tx 12-13 0x%x", 604 eht_cap->bw_20_tx_max_nss_for_mcs_12_and_13); 605 wma_nofl_debug("\t EHT MCS 80 rx 0-9 0x%x", 606 eht_cap->bw_le_80_rx_max_nss_for_mcs_0_to_9); 607 wma_nofl_debug("\t EHT MCS 80 tx 0-9 0x%x", 608 eht_cap->bw_le_80_tx_max_nss_for_mcs_0_to_9); 609 wma_nofl_debug("\t EHT MCS 80 rx 10-11 0x%x", 610 eht_cap->bw_le_80_rx_max_nss_for_mcs_10_and_11); 611 wma_nofl_debug("\t EHT MCS 80 tx 10-11 0x%x", 612 eht_cap->bw_le_80_tx_max_nss_for_mcs_10_and_11); 613 wma_nofl_debug("\t EHT MCS 80 rx 12-13 0x%x", 614 eht_cap->bw_le_80_rx_max_nss_for_mcs_12_and_13); 615 wma_nofl_debug("\t EHT MCS 80 tx 12-13 0x%x", 616 eht_cap->bw_le_80_tx_max_nss_for_mcs_12_and_13); 617 wma_nofl_debug("\t EHT MCS 160 rx 0-9 0x%x", 618 eht_cap->bw_160_rx_max_nss_for_mcs_0_to_9); 619 wma_nofl_debug("\t EHT MCS 160 tx 0-9 0x%x", 620 eht_cap->bw_160_tx_max_nss_for_mcs_0_to_9); 621 wma_nofl_debug("\t EHT MCS 160 rx 10-11 0x%x", 622 eht_cap->bw_160_rx_max_nss_for_mcs_10_and_11); 623 wma_nofl_debug("\t EHT MCS 160 tx 10-11 0x%x", 624 eht_cap->bw_160_tx_max_nss_for_mcs_10_and_11); 625 wma_nofl_debug("\t EHT MCS 160 rx 12-13 0x%x", 626 eht_cap->bw_160_rx_max_nss_for_mcs_12_and_13); 627 wma_nofl_debug("\t EHT MCS 160 rx 12-13 0x%x", 628 eht_cap->bw_160_tx_max_nss_for_mcs_12_and_13); 629 wma_nofl_debug("\t EHT MCS 320 rx 0-9 0x%x", 630 eht_cap->bw_320_rx_max_nss_for_mcs_0_to_9); 631 wma_nofl_debug("\t EHT MCS 320 tx 0-9 0x%x", 632 eht_cap->bw_320_tx_max_nss_for_mcs_0_to_9); 633 wma_nofl_debug("\t EHT MCS 320 rx 10-11 0x%x", 634 eht_cap->bw_320_rx_max_nss_for_mcs_10_and_11); 635 wma_nofl_debug("\t EHT MCS 320 tx 10-11 0x%x", 636 eht_cap->bw_320_tx_max_nss_for_mcs_10_and_11); 637 wma_nofl_debug("\t EHT MCS 320 rx 12-13 0x%x", 638 eht_cap->bw_320_rx_max_nss_for_mcs_12_and_13); 639 wma_nofl_debug("\t EHT MCS 320 tx 12-13 0x%x", 640 eht_cap->bw_320_tx_max_nss_for_mcs_12_and_13); 641 } 642 643 void wma_print_eht_phy_cap(uint32_t *phy_cap) 644 { 645 wma_debug("EHT PHY Capabilities:"); 646 647 wma_nofl_debug("\t320 MHz In 6 GHz: 0x%01x", 648 WMI_EHTCAP_PHY_320MHZIN6GHZ_GET(phy_cap)); 649 wma_nofl_debug("\t242-tone RU In BW Wider Than 20 MHz: 0x%01x", 650 WMI_EHTCAP_PHY_242TONERUBWLT20MHZ_GET(phy_cap)); 651 wma_nofl_debug("\tNDP With 4x EHT-LTF And 3.2 us GI: 0x%01x", 652 WMI_EHTCAP_PHY_NDP4XEHTLTFAND320NSGI_GET(phy_cap)); 653 wma_nofl_debug("\tPartial Bandwidth UL MU-MIMO: 0x%01x", 654 WMI_EHTCAP_PHY_PARTIALBWULMU_GET(phy_cap)); 655 wma_nofl_debug("\tSU Beamformer: 0x%01x", 656 WMI_EHTCAP_PHY_SUBFMR_GET(phy_cap)); 657 wma_nofl_debug("\tSU Beamformee: 0x%01x", 658 WMI_EHTCAP_PHY_SUBFME_GET(phy_cap)); 659 wma_nofl_debug("\tBeamformee SS <= 80 MHz: 0x%03x", 660 WMI_EHTCAP_PHY_BFMESSLT80MHZ_GET(phy_cap)); 661 wma_nofl_debug("\tBeamformee SS = 160 MHz: 0x%03x", 662 WMI_EHTCAP_PHY_BFMESS160MHZ_GET(phy_cap)); 663 wma_nofl_debug("\tBeamformee SS = 320 MHz: 0x%03x", 664 WMI_EHTCAP_PHY_BFMESS320MHZ_GET(phy_cap)); 665 wma_nofl_debug("\tNumber Of Sounding Dimensions <= 80 MHz: 0x%03x", 666 WMI_EHTCAP_PHY_NUMSOUNDLT80MHZ_GET(phy_cap)); 667 wma_nofl_debug("\tNumber Of Sounding Dimensions = 160 MHz: 0x%03x", 668 WMI_EHTCAP_PHY_NUMSOUND160MHZ_GET(phy_cap)); 669 wma_nofl_debug("\tNumber Of Sounding Dimensions = 320 MHz: 0x%03x", 670 WMI_EHTCAP_PHY_NUMSOUND320MHZ_GET(phy_cap)); 671 wma_nofl_debug("\tNg = 16 SU Feedback: 0x%01x", 672 WMI_EHTCAP_PHY_NG16SUFB_GET(phy_cap)); 673 wma_nofl_debug("\tNg = 16 MU Feedback: 0x%01x", 674 WMI_EHTCAP_PHY_NG16MUFB_GET(phy_cap)); 675 wma_nofl_debug("\tCodebook Size 4 2 SU Feedback: 0x%01x", 676 WMI_EHTCAP_PHY_CODBK42SUFB_GET(phy_cap)); 677 wma_nofl_debug("\tCodebook Size 7 5 MU Feedback: 0x%01x", 678 WMI_EHTCAP_PHY_CODBK75MUFB_GET(phy_cap)); 679 wma_nofl_debug("\tTriggered SU Beamforming Feedback: 0x%01x", 680 WMI_EHTCAP_PHY_TRIGSUBFFB_GET(phy_cap)); 681 wma_nofl_debug("\tTriggered MU Beamforming Partial BW Feedback: 0x%01x", 682 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_GET(phy_cap)); 683 wma_nofl_debug("\tTriggered CQI Feedback: 0x%01x", 684 WMI_EHTCAP_PHY_TRIGCQIFB_GET(phy_cap)); 685 wma_nofl_debug("\tPartial Bandwidth DL MU-MIMO: 0x%01x", 686 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_GET(phy_cap)); 687 wma_nofl_debug("\tPSR-Based SR: 0x%01x", 688 WMI_EHTCAP_PHY_PSRSR_GET(phy_cap)); 689 wma_nofl_debug("\tPower Boost Factor: 0x%01x", 690 WMI_EHTCAP_PHY_PWRBSTFACTOR_GET(phy_cap)); 691 wma_nofl_debug("\tMU PPDU With 4x EHT-LTF 0.8 us GI: 0x%01x", 692 WMI_EHTCAP_PHY_4XEHTLTFAND800NSGI_GET(phy_cap)); 693 wma_nofl_debug("\tMax Nc: 0x%04x", WMI_EHTCAP_PHY_MAXNC_GET(phy_cap)); 694 wma_nofl_debug("\tNon-Triggered CQI Feedback: 0x%01x", 695 WMI_EHTCAP_PHY_NONTRIGCQIFB_GET(phy_cap)); 696 wma_nofl_debug("\tTx 1024-QAM 4096-QAM < 242-tone RU: 0x%01x", 697 WMI_EHTCAP_PHY_TX1024AND4096QAMLS242TONERU_GET(phy_cap)); 698 wma_nofl_debug("\tRx 1024-QAM 4096-QAM < 242-tone RU: 0x%01x", 699 WMI_EHTCAP_PHY_RX1024AND4096QAMLS242TONERU_GET(phy_cap)); 700 wma_nofl_debug("\tPPE Thresholds Present: 0x%01x", 701 WMI_EHTCAP_PHY_PPETHRESPRESENT_GET(phy_cap)); 702 wma_nofl_debug("\tCommon Nominal Packet Padding: 0x%02x", 703 WMI_EHTCAP_PHY_CMNNOMPKTPAD_GET(phy_cap)); 704 wma_nofl_debug("\tMaximum Number Of Supported EHT-LTFs: 0x%05x", 705 WMI_EHTCAP_PHY_MAXNUMEHTLTF_GET(phy_cap)); 706 wma_nofl_debug("\tSupport of MCS 15: 0x%04x", 707 WMI_EHTCAP_PHY_SUPMCS15_GET(phy_cap)); 708 wma_nofl_debug("\tSupport Of EHT DUP In 6 GHz: 0x%01x", 709 WMI_EHTCAP_PHY_EHTDUPIN6GHZ_GET(phy_cap)); 710 wma_nofl_debug("\t20 MHz STA RX NDP With Wider BW: 0x%01x", 711 WMI_EHTCAP_PHY_20MHZOPSTARXNDPWIDERBW_GET(phy_cap)); 712 wma_nofl_debug("\tNon-OFDMA UL MU-MIMO BW <= 80 MHz: 0x%01x", 713 WMI_EHTCAP_PHY_NONOFDMAULMUMIMOLT80MHZ_GET(phy_cap)); 714 wma_nofl_debug("\tNon-OFDMA UL MU-MIMO BW = 160 MHz: 0x%01x", 715 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO160MHZ_GET(phy_cap)); 716 wma_nofl_debug("\tNon-OFDMA UL MU-MIMO BW = 320 MHz: 0x%01x", 717 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO320MHZ_GET(phy_cap)); 718 wma_nofl_debug("\tMU Beamformer BW <= 80 MHz: 0x%01x", 719 WMI_EHTCAP_PHY_MUBFMRLT80MHZ_GET(phy_cap)); 720 wma_nofl_debug("\tMU Beamformer BW = 160 MHz: 0x%01x", 721 WMI_EHTCAP_PHY_MUBFMR160MHZ_GET(phy_cap)); 722 wma_nofl_debug("\tMU Beamformer BW = 320 MHz: 0x%01x", 723 WMI_EHTCAP_PHY_MUBFMR320MHZ_GET(phy_cap)); 724 wma_nofl_debug("\tTB sounding feedback rate limit: 0x%01x", 725 WMI_EHTCAP_PHY_TBSUNDFBRATELIMIT_GET(phy_cap)); 726 wma_nofl_debug("\tRx 1024-QAM in wider bandwidth DL OFDMA support: 0x%01x", 727 WMI_EHTCAP_PHY_RX1024QAMWIDERBWDLOFDMA_GET(phy_cap)); 728 wma_nofl_debug("\tRx 4096-QAM in wider bandwidth DL OFDMA support: 0x%01x", 729 WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(phy_cap)); 730 } 731 732 void wma_print_eht_mac_cap(uint32_t *mac_cap) 733 { 734 wma_debug("EHT MAC Capabilities:"); 735 736 wma_nofl_debug("\tEPCS Priority Access: 0x%01x", 737 WMI_EHTCAP_MAC_EPCSPRIACCESS_GET(mac_cap)); 738 wma_nofl_debug("\tOM Control: 0x%01x", 739 WMI_EHTCAP_MAC_EHTOMCTRL_GET(mac_cap)); 740 wma_nofl_debug("\tTriggered TXOP Sharing mode 1 support: 0x%01x", 741 WMI_EHTCAP_MAC_TRIGTXOPMODE1_GET(mac_cap)); 742 wma_nofl_debug("\tTriggered TXOP Sharing mode 2 support: 0x%01x", 743 WMI_EHTCAP_MAC_TRIGTXOPMODE2_GET(mac_cap)); 744 wma_nofl_debug("\tRestricted TWT support: 0x%01x", 745 WMI_EHTCAP_MAC_RESTRICTTWT_GET(mac_cap)); 746 wma_nofl_debug("\tSCS Traffic Description Support: 0x%01x", 747 WMI_EHTCAP_MAC_SCSTRAFFICDESC_GET(mac_cap)); 748 wma_nofl_debug("\tMaximum MPDU Length: 0x%01x", 749 WMI_EHTCAP_MAC_MAXMPDULEN_GET(mac_cap)); 750 } 751 752 void wma_print_eht_op(tDot11fIEeht_op *eht_ops) 753 { 754 } 755 756 void wma_populate_peer_eht_cap(struct peer_assoc_params *peer, 757 tpAddStaParams params) 758 { 759 tDot11fIEeht_cap *eht_cap = ¶ms->eht_config; 760 uint32_t *phy_cap = peer->peer_eht_cap_phyinfo; 761 uint32_t *mac_cap = peer->peer_eht_cap_macinfo; 762 struct supported_rates *rates; 763 764 if (!params->eht_capable) 765 return; 766 767 peer->eht_flag = 1; 768 peer->qos_flag = 1; 769 770 /* EHT MAC Capabilities */ 771 WMI_EHTCAP_MAC_EPCSPRIACCESS_SET(mac_cap, eht_cap->epcs_pri_access); 772 WMI_EHTCAP_MAC_EHTOMCTRL_SET(mac_cap, eht_cap->eht_om_ctl); 773 WMI_EHTCAP_MAC_TRIGTXOPMODE1_SET(mac_cap, 774 eht_cap->triggered_txop_sharing_mode1); 775 WMI_EHTCAP_MAC_TRIGTXOPMODE2_SET(mac_cap, 776 eht_cap->triggered_txop_sharing_mode2); 777 WMI_EHTCAP_MAC_RESTRICTTWT_SET(mac_cap, 778 eht_cap->restricted_twt); 779 WMI_EHTCAP_MAC_SCSTRAFFICDESC_SET(mac_cap, 780 eht_cap->scs_traffic_desc); 781 WMI_EHTCAP_MAC_MAXMPDULEN_SET(mac_cap, 782 eht_cap->max_mpdu_len); 783 WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_SET(mac_cap, 784 eht_cap->max_a_mpdu_len_exponent_ext); 785 WMI_EHTCAP_MAC_TRS_SUPPORT_SET(mac_cap, 786 eht_cap->eht_trs_support); 787 WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_SET(mac_cap, 788 eht_cap->txop_return_support_txop_share_m2); 789 790 /* EHT PHY Capabilities */ 791 WMI_EHTCAP_PHY_320MHZIN6GHZ_SET(phy_cap, eht_cap->support_320mhz_6ghz); 792 WMI_EHTCAP_PHY_242TONERUBWLT20MHZ_SET(phy_cap, 793 eht_cap->ru_242tone_wt_20mhz); 794 WMI_EHTCAP_PHY_NDP4XEHTLTFAND320NSGI_SET( 795 phy_cap, eht_cap->ndp_4x_eht_ltf_3dot2_us_gi); 796 WMI_EHTCAP_PHY_PARTIALBWULMU_SET(phy_cap, eht_cap->partial_bw_mu_mimo); 797 WMI_EHTCAP_PHY_SUBFMR_SET(phy_cap, eht_cap->su_beamformer); 798 WMI_EHTCAP_PHY_SUBFME_SET(phy_cap, eht_cap->su_beamformee); 799 WMI_EHTCAP_PHY_BFMESSLT80MHZ_SET(phy_cap, eht_cap->bfee_ss_le_80mhz); 800 WMI_EHTCAP_PHY_BFMESS160MHZ_SET(phy_cap, eht_cap->bfee_ss_160mhz); 801 WMI_EHTCAP_PHY_BFMESS320MHZ_SET(phy_cap, eht_cap->bfee_ss_320mhz); 802 WMI_EHTCAP_PHY_NUMSOUNDLT80MHZ_SET( 803 phy_cap, eht_cap->num_sounding_dim_le_80mhz); 804 WMI_EHTCAP_PHY_NUMSOUND160MHZ_SET(phy_cap, 805 eht_cap->num_sounding_dim_160mhz); 806 WMI_EHTCAP_PHY_NUMSOUND320MHZ_SET(phy_cap, 807 eht_cap->num_sounding_dim_320mhz); 808 WMI_EHTCAP_PHY_NG16SUFB_SET(phy_cap, eht_cap->ng_16_su_feedback); 809 WMI_EHTCAP_PHY_NG16MUFB_SET(phy_cap, eht_cap->ng_16_mu_feedback); 810 WMI_EHTCAP_PHY_CODBK42SUFB_SET(phy_cap, eht_cap->cb_sz_4_2_su_feedback); 811 WMI_EHTCAP_PHY_CODBK75MUFB_SET(phy_cap, eht_cap->cb_sz_7_5_su_feedback); 812 WMI_EHTCAP_PHY_TRIGSUBFFB_SET(phy_cap, 813 eht_cap->trig_su_bforming_feedback); 814 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_SET( 815 phy_cap, eht_cap->trig_mu_bforming_partial_bw_feedback); 816 WMI_EHTCAP_PHY_TRIGCQIFB_SET(phy_cap, eht_cap->triggered_cqi_feedback); 817 WMI_EHTCAP_PHY_PARTBWDLMUMIMO_SET(phy_cap, 818 eht_cap->partial_bw_dl_mu_mimo); 819 WMI_EHTCAP_PHY_PSRSR_SET(phy_cap, eht_cap->psr_based_sr); 820 WMI_EHTCAP_PHY_PWRBSTFACTOR_SET(phy_cap, eht_cap->power_boost_factor); 821 WMI_EHTCAP_PHY_4XEHTLTFAND800NSGI_SET( 822 phy_cap, eht_cap->eht_mu_ppdu_4x_ltf_0_8_us_gi); 823 WMI_EHTCAP_PHY_MAXNC_SET(phy_cap, eht_cap->max_nc); 824 WMI_EHTCAP_PHY_NONTRIGCQIFB_SET(phy_cap, 825 eht_cap->non_trig_cqi_feedback); 826 WMI_EHTCAP_PHY_TX1024AND4096QAMLS242TONERU_SET( 827 phy_cap, eht_cap->tx_1024_4096_qam_lt_242_tone_ru); 828 WMI_EHTCAP_PHY_RX1024AND4096QAMLS242TONERU_SET( 829 phy_cap, eht_cap->rx_1024_4096_qam_lt_242_tone_ru); 830 WMI_EHTCAP_PHY_PPETHRESPRESENT_SET(phy_cap, eht_cap->ppet_present); 831 WMI_EHTCAP_PHY_CMNNOMPKTPAD_SET(phy_cap, 832 eht_cap->common_nominal_pkt_padding); 833 WMI_EHTCAP_PHY_MAXNUMEHTLTF_SET(phy_cap, eht_cap->max_num_eht_ltf); 834 WMI_EHTCAP_PHY_SUPMCS15_SET(phy_cap, eht_cap->mcs_15); 835 WMI_EHTCAP_PHY_EHTDUPIN6GHZ_SET(phy_cap, eht_cap->eht_dup_6ghz); 836 WMI_EHTCAP_PHY_20MHZOPSTARXNDPWIDERBW_SET( 837 phy_cap, eht_cap->op_sta_rx_ndp_wider_bw_20mhz); 838 WMI_EHTCAP_PHY_NONOFDMAULMUMIMOLT80MHZ_SET( 839 phy_cap, eht_cap->non_ofdma_ul_mu_mimo_le_80mhz); 840 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO160MHZ_SET( 841 phy_cap, eht_cap->non_ofdma_ul_mu_mimo_160mhz); 842 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO320MHZ_SET( 843 phy_cap, eht_cap->non_ofdma_ul_mu_mimo_320mhz); 844 WMI_EHTCAP_PHY_MUBFMRLT80MHZ_SET(phy_cap, eht_cap->mu_bformer_le_80mhz); 845 WMI_EHTCAP_PHY_MUBFMR160MHZ_SET(phy_cap, eht_cap->mu_bformer_160mhz); 846 WMI_EHTCAP_PHY_MUBFMR320MHZ_SET(phy_cap, eht_cap->mu_bformer_320mhz); 847 WMI_EHTCAP_PHY_TBSUNDFBRATELIMIT_SET(phy_cap, 848 eht_cap->tb_sounding_feedback_rl); 849 WMI_EHTCAP_PHY_RX1024QAMWIDERBWDLOFDMA_SET(phy_cap, 850 eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma); 851 WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(phy_cap, 852 eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma); 853 854 peer->peer_eht_mcs_count = 0; 855 rates = ¶ms->supportedRates; 856 857 /* 858 * Convert eht mcs to firmware understandable format 859 * BITS 0:3 indicates support for mcs 0 to 7 860 * BITS 4:7 indicates support for mcs 8 and 9 861 * BITS 8:11 indicates support for mcs 10 and 11 862 * BITS 12:15 indicates support for mcs 12 and 13 863 */ 864 switch (params->ch_width) { 865 case CH_WIDTH_320MHZ: 866 peer->peer_eht_mcs_count++; 867 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 868 0, 4, rates->bw_320_rx_max_nss_for_mcs_0_to_9); 869 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 870 0, 4, rates->bw_320_tx_max_nss_for_mcs_0_to_9); 871 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 872 4, 4, rates->bw_320_rx_max_nss_for_mcs_0_to_9); 873 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 874 4, 4, rates->bw_320_tx_max_nss_for_mcs_0_to_9); 875 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 876 8, 4, rates->bw_320_rx_max_nss_for_mcs_10_and_11); 877 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 878 8, 4, rates->bw_320_tx_max_nss_for_mcs_10_and_11); 879 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 880 12, 4, rates->bw_320_rx_max_nss_for_mcs_12_and_13); 881 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2], 882 12, 4, rates->bw_320_tx_max_nss_for_mcs_12_and_13); 883 fallthrough; 884 case CH_WIDTH_160MHZ: 885 peer->peer_eht_mcs_count++; 886 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 887 0, 4, rates->bw_160_rx_max_nss_for_mcs_0_to_9); 888 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 889 0, 4, rates->bw_160_tx_max_nss_for_mcs_0_to_9); 890 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 891 4, 4, rates->bw_160_rx_max_nss_for_mcs_0_to_9); 892 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 893 4, 4, rates->bw_160_tx_max_nss_for_mcs_0_to_9); 894 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 895 8, 4, rates->bw_160_rx_max_nss_for_mcs_10_and_11); 896 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 897 8, 4, rates->bw_160_rx_max_nss_for_mcs_10_and_11); 898 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 899 12, 4, rates->bw_160_rx_max_nss_for_mcs_12_and_13); 900 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1], 901 12, 4, rates->bw_160_tx_max_nss_for_mcs_12_and_13); 902 fallthrough; 903 case CH_WIDTH_80MHZ: 904 case CH_WIDTH_40MHZ: 905 peer->peer_eht_mcs_count++; 906 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 907 0, 4, rates->bw_le_80_rx_max_nss_for_mcs_0_to_9); 908 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 909 0, 4, rates->bw_le_80_tx_max_nss_for_mcs_0_to_9); 910 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 911 4, 4, rates->bw_le_80_rx_max_nss_for_mcs_0_to_9); 912 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 913 4, 4, rates->bw_le_80_tx_max_nss_for_mcs_0_to_9); 914 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 915 8, 4, rates->bw_le_80_rx_max_nss_for_mcs_10_and_11); 916 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 917 8, 4, rates->bw_le_80_tx_max_nss_for_mcs_10_and_11); 918 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 919 12, 4, rates->bw_le_80_rx_max_nss_for_mcs_12_and_13); 920 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 921 12, 4, rates->bw_le_80_rx_max_nss_for_mcs_12_and_13); 922 break; 923 case CH_WIDTH_20MHZ: 924 peer->peer_eht_mcs_count++; 925 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 926 0, 4, rates->bw_20_rx_max_nss_for_mcs_0_to_7); 927 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 928 0, 4, rates->bw_20_tx_max_nss_for_mcs_0_to_7); 929 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 930 4, 4, rates->bw_20_rx_max_nss_for_mcs_8_and_9); 931 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 932 4, 4, rates->bw_20_tx_max_nss_for_mcs_8_and_9); 933 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 934 8, 4, rates->bw_20_rx_max_nss_for_mcs_10_and_11); 935 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 936 8, 4, rates->bw_20_tx_max_nss_for_mcs_10_and_11); 937 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 938 12, 4, rates->bw_20_rx_max_nss_for_mcs_12_and_13); 939 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0], 940 12, 4, rates->bw_20_tx_max_nss_for_mcs_12_and_13); 941 break; 942 default: 943 break; 944 } 945 946 wma_print_eht_cap(eht_cap); 947 wma_debug("Peer EHT Capabilities:"); 948 wma_print_eht_phy_cap(phy_cap); 949 wma_print_eht_mac_cap(mac_cap); 950 } 951 952 void wma_vdev_set_eht_bss_params(tp_wma_handle wma, uint8_t vdev_id, 953 struct vdev_mlme_eht_ops_info *eht_info) 954 { 955 if (!eht_info->eht_ops) 956 return; 957 } 958 959 QDF_STATUS wma_get_eht_capabilities(struct eht_capability *eht_cap) 960 { 961 tp_wma_handle wma_handle; 962 963 wma_handle = cds_get_context(QDF_MODULE_ID_WMA); 964 if (!wma_handle) 965 return QDF_STATUS_E_FAILURE; 966 967 qdf_mem_copy(eht_cap->phy_cap, 968 &wma_handle->eht_cap.phy_cap, 969 WMI_MAX_EHTCAP_PHY_SIZE); 970 eht_cap->mac_cap = wma_handle->eht_cap.mac_cap; 971 return QDF_STATUS_SUCCESS; 972 } 973 974 void wma_set_peer_assoc_params_bw_320(struct peer_assoc_params *params, 975 enum phy_ch_width ch_width) 976 { 977 if (ch_width == CH_WIDTH_320MHZ) 978 params->bw_320 = 1; 979 } 980 981 void wma_set_eht_txbf_cfg(struct mac_context *mac, uint8_t vdev_id) 982 { 983 wma_set_eht_txbf_params( 984 vdev_id, mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformer, 985 mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformee, 986 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_le_80mhz || 987 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_160mhz || 988 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_320mhz); 989 } 990 991 void wma_set_eht_txbf_params(uint8_t vdev_id, bool su_bfer, 992 bool su_bfee, bool mu_bfer) 993 { 994 uint32_t ehtmu_mode = 0; 995 QDF_STATUS status; 996 tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA); 997 998 if (!wma) 999 return; 1000 1001 if (su_bfer) 1002 WMI_VDEV_EHT_SUBFER_ENABLE(ehtmu_mode); 1003 if (su_bfee) { 1004 WMI_VDEV_EHT_SUBFEE_ENABLE(ehtmu_mode); 1005 WMI_VDEV_EHT_MUBFEE_ENABLE(ehtmu_mode); 1006 } 1007 if (mu_bfer) 1008 WMI_VDEV_EHT_MUBFER_ENABLE(ehtmu_mode); 1009 1010 WMI_VDEV_EHT_DLOFDMA_ENABLE(ehtmu_mode); 1011 WMI_VDEV_EHT_ULOFDMA_ENABLE(ehtmu_mode); 1012 1013 status = wma_vdev_set_param(wma->wmi_handle, vdev_id, 1014 wmi_vdev_param_set_eht_mu_mode, ehtmu_mode); 1015 wma_debug("set EHTMU_MODE (ehtmu_mode = 0x%x)", ehtmu_mode); 1016 1017 if (QDF_IS_STATUS_ERROR(status)) 1018 wma_err("failed to set EHTMU_MODE(status = %d)", status); 1019 } 1020 1021 QDF_STATUS wma_set_bss_rate_flags_eht(enum tx_rate_info *rate_flags, 1022 struct bss_params *add_bss) 1023 { 1024 if (!add_bss->eht_capable) 1025 return QDF_STATUS_E_NOSUPPORT; 1026 1027 *rate_flags |= wma_get_eht_rate_flags(add_bss->ch_width); 1028 1029 wma_debug("ehe_capable %d rate_flags 0x%x", add_bss->eht_capable, 1030 *rate_flags); 1031 return QDF_STATUS_SUCCESS; 1032 } 1033 1034 bool wma_get_bss_eht_capable(struct bss_params *add_bss) 1035 { 1036 return add_bss->eht_capable; 1037 } 1038 1039 enum tx_rate_info wma_get_eht_rate_flags(enum phy_ch_width ch_width) 1040 { 1041 enum tx_rate_info rate_flags = 0; 1042 1043 if (ch_width == CH_WIDTH_320MHZ) 1044 rate_flags |= TX_RATE_EHT320 | TX_RATE_EHT160 | 1045 TX_RATE_EHT80 | TX_RATE_EHT40 | TX_RATE_EHT20; 1046 else if (ch_width == CH_WIDTH_160MHZ || ch_width == CH_WIDTH_80P80MHZ) 1047 rate_flags |= TX_RATE_EHT160 | TX_RATE_EHT80 | TX_RATE_EHT40 | 1048 TX_RATE_EHT20; 1049 else if (ch_width == CH_WIDTH_80MHZ) 1050 rate_flags |= TX_RATE_EHT80 | TX_RATE_EHT40 | TX_RATE_EHT20; 1051 else if (ch_width) 1052 rate_flags |= TX_RATE_EHT40 | TX_RATE_EHT20; 1053 else 1054 rate_flags |= TX_RATE_EHT20; 1055 1056 return rate_flags; 1057 } 1058 1059 uint16_t wma_match_eht_rate(uint16_t raw_rate, 1060 enum tx_rate_info rate_flags, 1061 uint8_t *nss, uint8_t *dcm, 1062 enum txrate_gi *guard_interval, 1063 enum tx_rate_info *mcs_rate_flag, 1064 uint8_t *p_index) 1065 { 1066 uint8_t index; 1067 uint8_t dcm_index_max = 1; 1068 uint8_t dcm_index; 1069 uint16_t match_rate = 0; 1070 const uint16_t *nss1_rate; 1071 const uint16_t *nss2_rate; 1072 1073 *p_index = 0; 1074 if (!(rate_flags & (TX_RATE_EHT320 | TX_RATE_EHT160 | TX_RATE_EHT80 | 1075 TX_RATE_EHT40 | TX_RATE_EHT20))) 1076 return 0; 1077 1078 for (index = 0; index < MAX_EHT_MCS_IDX; index++) { 1079 dcm_index_max = IS_MCS_HAS_DCM_RATE(index) ? 2 : 1; 1080 for (dcm_index = 0; dcm_index < dcm_index_max; dcm_index++) { 1081 if (rate_flags & TX_RATE_EHT320) { 1082 nss1_rate = &eht_mcs_nss1[index].supported_eht320_rate[dcm_index][0]; 1083 nss2_rate = &eht_mcs_nss2[index].supported_eht320_rate[dcm_index][0]; 1084 match_rate = wma_mcs_rate_match(raw_rate, 1, 1085 nss1_rate, 1086 nss2_rate, 1087 nss, 1088 guard_interval); 1089 if (match_rate) 1090 goto rate_found; 1091 } 1092 if (rate_flags & TX_RATE_EHT160) { 1093 nss1_rate = &eht_mcs_nss1[index].supported_eht160_rate[dcm_index][0]; 1094 nss2_rate = &eht_mcs_nss2[index].supported_eht160_rate[dcm_index][0]; 1095 match_rate = wma_mcs_rate_match(raw_rate, 1, 1096 nss1_rate, 1097 nss2_rate, 1098 nss, 1099 guard_interval); 1100 if (match_rate) 1101 goto rate_found; 1102 } 1103 1104 if (rate_flags & (TX_RATE_EHT80 | TX_RATE_EHT160)) { 1105 nss1_rate = &eht_mcs_nss1[index].supported_eht80_rate[dcm_index][0]; 1106 nss2_rate = &eht_mcs_nss2[index].supported_eht80_rate[dcm_index][0]; 1107 /* check for he80 nss1/2 rate set */ 1108 match_rate = wma_mcs_rate_match(raw_rate, 1, 1109 nss1_rate, 1110 nss2_rate, 1111 nss, 1112 guard_interval); 1113 if (match_rate) { 1114 *mcs_rate_flag &= ~TX_RATE_EHT160; 1115 goto rate_found; 1116 } 1117 } 1118 1119 if (rate_flags & (TX_RATE_EHT40 | TX_RATE_EHT80 | 1120 TX_RATE_EHT160)) { 1121 nss1_rate = &eht_mcs_nss1[index].supported_eht40_rate[dcm_index][0]; 1122 nss2_rate = &eht_mcs_nss2[index].supported_eht40_rate[dcm_index][0]; 1123 match_rate = wma_mcs_rate_match(raw_rate, 1, 1124 nss1_rate, 1125 nss2_rate, 1126 nss, 1127 guard_interval); 1128 1129 if (match_rate) { 1130 *mcs_rate_flag &= ~(TX_RATE_EHT80 | 1131 TX_RATE_EHT160); 1132 goto rate_found; 1133 } 1134 } 1135 1136 if (rate_flags & (TX_RATE_EHT80 | TX_RATE_EHT40 | 1137 TX_RATE_EHT20 | TX_RATE_EHT160)) { 1138 nss1_rate = &eht_mcs_nss1[index].supported_eht20_rate[dcm_index][0]; 1139 nss2_rate = &eht_mcs_nss2[index].supported_eht20_rate[dcm_index][0]; 1140 match_rate = wma_mcs_rate_match(raw_rate, 1, 1141 nss1_rate, 1142 nss2_rate, 1143 nss, 1144 guard_interval); 1145 1146 if (match_rate) { 1147 *mcs_rate_flag &= TX_RATE_EHT20; 1148 goto rate_found; 1149 } 1150 } 1151 } 1152 } 1153 1154 rate_found: 1155 if (match_rate) { 1156 if (dcm_index == 1) 1157 *dcm = 1; 1158 *p_index = index; 1159 } 1160 return match_rate; 1161 } 1162 1163 QDF_STATUS 1164 wma_set_eht_txbf_vdev_params(struct mac_context *mac, uint32_t *mode) 1165 { 1166 uint32_t ehtmu_mode = 0; 1167 bool su_bfer = mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformer; 1168 bool su_bfee = mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformee; 1169 bool mu_bfer = 1170 (mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_le_80mhz || 1171 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_160mhz || 1172 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_320mhz); 1173 1174 if (su_bfer) 1175 WMI_VDEV_EHT_SUBFER_ENABLE(ehtmu_mode); 1176 if (su_bfee) { 1177 WMI_VDEV_EHT_SUBFEE_ENABLE(ehtmu_mode); 1178 WMI_VDEV_EHT_MUBFEE_ENABLE(ehtmu_mode); 1179 } 1180 if (mu_bfer) 1181 WMI_VDEV_EHT_MUBFER_ENABLE(ehtmu_mode); 1182 WMI_VDEV_EHT_DLOFDMA_ENABLE(ehtmu_mode); 1183 WMI_VDEV_EHT_ULOFDMA_ENABLE(ehtmu_mode); 1184 wma_debug("set EHTMU_MODE (ehtmu_mode = 0x%x)", 1185 ehtmu_mode); 1186 *mode = ehtmu_mode; 1187 1188 return QDF_STATUS_SUCCESS; 1189 } 1190 #endif 1191