1 /* 2 * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 28 #ifndef _HTT_TYPES__H_ 29 #define _HTT_TYPES__H_ 30 31 #include <osdep.h> /* uint16_t, dma_addr_t */ 32 #include <qdf_types.h> /* qdf_device_t */ 33 #include <qdf_lock.h> /* qdf_spinlock_t */ 34 #include <qdf_timer.h> /* qdf_timer_t */ 35 #include <qdf_atomic.h> /* qdf_atomic_inc */ 36 #include <qdf_nbuf.h> /* qdf_nbuf_t */ 37 #include <htc_api.h> /* HTC_PACKET */ 38 #include <ol_htt_api.h> 39 40 #define DEBUG_DMA_DONE 41 42 #define HTT_TX_MUTEX_TYPE qdf_spinlock_t 43 44 #ifdef QCA_TX_HTT2_SUPPORT 45 #ifndef HTC_TX_HTT2_MAX_SIZE 46 /* Should sync to the target's implementation. */ 47 #define HTC_TX_HTT2_MAX_SIZE (120) 48 #endif 49 #endif /* QCA_TX_HTT2_SUPPORT */ 50 51 52 struct htt_htc_pkt { 53 void *pdev_ctxt; 54 dma_addr_t nbuf_paddr; 55 HTC_PACKET htc_pkt; 56 uint16_t msdu_id; 57 }; 58 59 struct htt_htc_pkt_union { 60 union { 61 struct htt_htc_pkt pkt; 62 struct htt_htc_pkt_union *next; 63 } u; 64 }; 65 66 /* 67 * HTT host descriptor: 68 * Include the htt_tx_msdu_desc that gets downloaded to the target, 69 * but also include the HTC_FRAME_HDR and alignment padding that 70 * precede the htt_tx_msdu_desc. 71 * htc_send_data_pkt expects this header space at the front of the 72 * initial fragment (i.e. tx descriptor) that is downloaded. 73 */ 74 struct htt_host_tx_desc_t { 75 uint8_t htc_header[HTC_HEADER_LEN]; 76 /* force the tx_desc field to begin on a 4-byte boundary */ 77 union { 78 uint32_t dummy_force_align; 79 struct htt_tx_msdu_desc_t tx_desc; 80 } align32; 81 }; 82 83 struct htt_tx_mgmt_desc_buf { 84 qdf_nbuf_t msg_buf; 85 A_BOOL is_inuse; 86 qdf_nbuf_t mgmt_frm; 87 }; 88 89 struct htt_tx_mgmt_desc_ctxt { 90 struct htt_tx_mgmt_desc_buf *pool; 91 A_UINT32 pending_cnt; 92 }; 93 94 struct htt_list_node { 95 struct htt_list_node *prev; 96 struct htt_list_node *next; 97 }; 98 99 struct htt_rx_hash_entry { 100 A_UINT32 paddr; 101 qdf_nbuf_t netbuf; 102 A_UINT8 fromlist; 103 struct htt_list_node listnode; 104 #ifdef RX_HASH_DEBUG 105 A_UINT32 cookie; 106 #endif 107 }; 108 109 struct htt_rx_hash_bucket { 110 struct htt_list_node listhead; 111 struct htt_rx_hash_entry *entries; 112 struct htt_list_node freepool; 113 #ifdef RX_HASH_DEBUG 114 A_UINT32 count; 115 #endif 116 }; 117 118 /* IPA micro controller 119 wlan host driver 120 firmware shared memory structure */ 121 struct uc_shared_mem_t { 122 uint32_t *vaddr; 123 qdf_dma_addr_t paddr; 124 qdf_dma_mem_context(memctx); 125 }; 126 127 /* Micro controller datapath offload 128 * WLAN TX resources */ 129 struct htt_ipa_uc_tx_resource_t { 130 struct uc_shared_mem_t tx_ce_idx; 131 struct uc_shared_mem_t tx_comp_base; 132 133 uint32_t tx_comp_idx_paddr; 134 void **tx_buf_pool_vaddr_strg; 135 qdf_dma_addr_t *paddr_strg; 136 uint32_t alloc_tx_buf_cnt; 137 }; 138 139 /** 140 * struct htt_ipa_uc_rx_resource_t 141 * @rx_rdy_idx_paddr: rx ready index physical address 142 * @rx_ind_ring_base: rx indication ring base memory info 143 * @rx_ipa_prc_done_idx: rx process done index memory info 144 * @rx_ind_ring_size: rx process done ring size 145 * @rx2_rdy_idx_paddr: rx process done index physical address 146 * @rx2_ind_ring_base: rx process done indication ring base memory info 147 * @rx2_ipa_prc_done_idx: rx process done index memory info 148 * @rx2_ind_ring_size: rx process done ring size 149 */ 150 struct htt_ipa_uc_rx_resource_t { 151 qdf_dma_addr_t rx_rdy_idx_paddr; 152 struct uc_shared_mem_t rx_ind_ring_base; 153 struct uc_shared_mem_t rx_ipa_prc_done_idx; 154 uint32_t rx_ind_ring_size; 155 156 /* 2nd RX ring */ 157 qdf_dma_addr_t rx2_rdy_idx_paddr; 158 struct uc_shared_mem_t rx2_ind_ring_base; 159 struct uc_shared_mem_t rx2_ipa_prc_done_idx; 160 uint32_t rx2_ind_ring_size; 161 }; 162 163 /** 164 * struct ipa_uc_rx_ring_elem_t 165 * @rx_packet_paddr: rx packet physical address 166 * @vdev_id: virtual interface id 167 * @rx_packet_leng: packet length 168 */ 169 struct ipa_uc_rx_ring_elem_t { 170 qdf_dma_addr_t rx_packet_paddr; 171 uint32_t vdev_id; 172 uint32_t rx_packet_leng; 173 }; 174 175 struct htt_tx_credit_t { 176 qdf_atomic_t bus_delta; 177 qdf_atomic_t target_delta; 178 }; 179 180 #if defined(HELIUMPLUS_PADDR64) 181 /** 182 * msdu_ext_frag_desc: 183 * semantically, this is an array of 6 of 2-tuples of 184 * a 48-bit physical address and a 16 bit len field 185 * with the following layout: 186 * 31 16 8 0 187 * | p t r - l o w 3 2 | 188 * | len | ptr-7/16 | 189 */ 190 struct msdu_ext_frag_desc { 191 union { 192 uint64_t desc64; 193 struct { 194 uint32_t ptr_low; 195 uint32_t ptr_hi:16, 196 len:16; 197 } frag32; 198 } u; 199 }; 200 201 struct msdu_ext_desc_t { 202 struct qdf_tso_flags_t tso_flags; 203 struct msdu_ext_frag_desc frags[6]; 204 /* 205 u_int32_t frag_ptr0; 206 u_int32_t frag_len0; 207 u_int32_t frag_ptr1; 208 u_int32_t frag_len1; 209 u_int32_t frag_ptr2; 210 u_int32_t frag_len2; 211 u_int32_t frag_ptr3; 212 u_int32_t frag_len3; 213 u_int32_t frag_ptr4; 214 u_int32_t frag_len4; 215 u_int32_t frag_ptr5; 216 u_int32_t frag_len5; 217 */ 218 }; 219 #endif /* defined(HELIUMPLUS_PADDR64) */ 220 221 /** 222 * struct mon_channel 223 * @ch_num: Monitor mode capture channel number 224 * @ch_freq: channel frequency. 225 */ 226 struct mon_channel { 227 uint32_t ch_num; 228 uint32_t ch_freq; 229 }; 230 231 struct htt_pdev_t { 232 ol_pdev_handle ctrl_pdev; 233 ol_txrx_pdev_handle txrx_pdev; 234 HTC_HANDLE htc_pdev; 235 qdf_device_t osdev; 236 237 HTC_ENDPOINT_ID htc_tx_endpoint; 238 239 #ifdef QCA_TX_HTT2_SUPPORT 240 HTC_ENDPOINT_ID htc_tx_htt2_endpoint; 241 uint16_t htc_tx_htt2_max_size; 242 #endif /* QCA_TX_HTT2_SUPPORT */ 243 244 #ifdef ATH_11AC_TXCOMPACT 245 HTT_TX_MUTEX_TYPE txnbufq_mutex; 246 qdf_nbuf_queue_t txnbufq; 247 struct htt_htc_pkt_union *htt_htc_pkt_misclist; 248 #endif 249 250 struct htt_htc_pkt_union *htt_htc_pkt_freelist; 251 struct { 252 int is_high_latency; 253 int is_full_reorder_offload; 254 int default_tx_comp_req; 255 int ce_classify_enabled; 256 uint8_t is_first_wakeup_packet; 257 } cfg; 258 struct { 259 uint8_t major; 260 uint8_t minor; 261 } tgt_ver; 262 #if defined(HELIUMPLUS_PADDR64) 263 struct { 264 u_int8_t major; 265 u_int8_t minor; 266 } wifi_ip_ver; 267 #endif /* defined(HELIUMPLUS_PADDR64) */ 268 struct { 269 struct { 270 /* 271 * Ring of network buffer objects - 272 * This ring is used exclusively by the host SW. 273 * This ring mirrors the dev_addrs_ring that is shared 274 * between the host SW and the MAC HW. 275 * The host SW uses this netbufs ring to locate the nw 276 * buffer objects whose data buffers the HW has filled. 277 */ 278 qdf_nbuf_t *netbufs_ring; 279 /* 280 * Ring of buffer addresses - 281 * This ring holds the "physical" device address of the 282 * rx buffers the host SW provides for MAC HW to fill. 283 */ 284 #if HTT_PADDR64 285 uint64_t *paddrs_ring; 286 #else /* ! HTT_PADDR64 */ 287 uint32_t *paddrs_ring; 288 #endif 289 qdf_dma_mem_context(memctx); 290 } buf; 291 /* 292 * Base address of ring, as a "physical" device address rather 293 * than a CPU address. 294 */ 295 qdf_dma_addr_t base_paddr; 296 int32_t size; /* how many elems in the ring (power of 2) */ 297 uint32_t size_mask; /* size - 1, at least 16 bits long */ 298 299 int fill_level; /* how many rx buffers to keep in the ring */ 300 int fill_cnt; /* # of rx buffers (full+empty) in the ring */ 301 302 /* 303 * target_idx - 304 * Without reorder offload: 305 * not used 306 * With reorder offload: 307 * points to the location in the rx ring from which rx buffers 308 * are available to copy into the MAC DMA ring 309 */ 310 struct { 311 uint32_t *vaddr; 312 qdf_dma_addr_t paddr; 313 qdf_dma_mem_context(memctx); 314 } target_idx; 315 316 /* 317 * alloc_idx/host_idx - 318 * Without reorder offload: 319 * where HTT SW has deposited empty buffers 320 * This is allocated in consistent mem, so that the FW can read 321 * this variable, and program the HW's FW_IDX reg with the value 322 * of this shadow register 323 * With reorder offload: 324 * points to the end of the available free rx buffers 325 */ 326 struct { 327 uint32_t *vaddr; 328 qdf_dma_addr_t paddr; 329 qdf_dma_mem_context(memctx); 330 } alloc_idx; 331 332 /* sw_rd_idx - 333 * where HTT SW has processed bufs filled by rx MAC DMA */ 334 struct { 335 unsigned msdu_desc; 336 unsigned msdu_payld; 337 } sw_rd_idx; 338 339 /* 340 * refill_retry_timer - timer triggered when the ring is not 341 * refilled to the level expected 342 */ 343 qdf_timer_t refill_retry_timer; 344 345 /* 346 * refill_ref_cnt - ref cnt for Rx buffer replenishment - this 347 * variable is used to guarantee that only one thread tries 348 * to replenish Rx ring. 349 */ 350 qdf_atomic_t refill_ref_cnt; 351 #ifdef DEBUG_DMA_DONE 352 uint32_t dbg_initial_msdu_payld; 353 uint32_t dbg_mpdu_range; 354 uint32_t dbg_mpdu_count; 355 uint32_t dbg_ring_idx; 356 uint32_t dbg_refill_cnt; 357 uint32_t dbg_sync_success; 358 #endif 359 #ifdef HTT_RX_RESTORE 360 int rx_reset; 361 uint8_t htt_rx_restore; 362 #endif 363 qdf_spinlock_t rx_hash_lock; 364 struct htt_rx_hash_bucket **hash_table; 365 uint32_t listnode_offset; 366 } rx_ring; 367 #ifdef CONFIG_HL_SUPPORT 368 int rx_desc_size_hl; 369 #endif 370 long rx_fw_desc_offset; 371 int rx_mpdu_range_offset_words; 372 int rx_ind_msdu_byte_idx; 373 374 struct { 375 int size; /* of each HTT tx desc */ 376 uint16_t pool_elems; 377 uint16_t alloc_cnt; 378 struct qdf_mem_multi_page_t desc_pages; 379 uint32_t *freelist; 380 qdf_dma_mem_context(memctx); 381 } tx_descs; 382 #if defined(HELIUMPLUS_PADDR64) 383 struct { 384 int size; /* of each Fragment/MSDU-Ext descriptor */ 385 int pool_elems; 386 struct qdf_mem_multi_page_t desc_pages; 387 qdf_dma_mem_context(memctx); 388 } frag_descs; 389 #endif /* defined(HELIUMPLUS_PADDR64) */ 390 391 int download_len; 392 void (*tx_send_complete_part2)(void *pdev, A_STATUS status, 393 qdf_nbuf_t msdu, uint16_t msdu_id); 394 395 HTT_TX_MUTEX_TYPE htt_tx_mutex; 396 397 struct { 398 int htc_err_cnt; 399 } stats; 400 #ifdef CONFIG_HL_SUPPORT 401 int cur_seq_num_hl; 402 #endif 403 struct htt_tx_mgmt_desc_ctxt tx_mgmt_desc_ctxt; 404 struct targetdef_s *targetdef; 405 struct ce_reg_def *target_ce_def; 406 407 struct htt_ipa_uc_tx_resource_t ipa_uc_tx_rsc; 408 struct htt_ipa_uc_rx_resource_t ipa_uc_rx_rsc; 409 410 struct htt_tx_credit_t htt_tx_credit; 411 412 #ifdef DEBUG_RX_RING_BUFFER 413 struct rx_buf_debug *rx_buff_list; 414 qdf_spinlock_t rx_buff_list_lock; 415 int rx_buff_index; 416 #endif 417 418 /* callback function for packetdump */ 419 tp_rx_pkt_dump_cb rx_pkt_dump_cb; 420 421 struct mon_channel mon_ch_info; 422 }; 423 424 #define HTT_EPID_GET(_htt_pdev_hdl) \ 425 (((struct htt_pdev_t *)(_htt_pdev_hdl))->htc_tx_endpoint) 426 427 #if defined(HELIUMPLUS_PADDR64) 428 #define HTT_WIFI_IP(pdev, x, y) (((pdev)->wifi_ip_ver.major == (x)) && \ 429 ((pdev)->wifi_ip_ver.minor == (y))) 430 431 #define HTT_SET_WIFI_IP(pdev, x, y) (((pdev)->wifi_ip_ver.major = (x)) && \ 432 ((pdev)->wifi_ip_ver.minor = (y))) 433 #endif /* defined(HELIUMPLUS_PADDR64) */ 434 435 #endif /* _HTT_TYPES__H_ */ 436