1 /* 2 * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _WMI_UNIFIED_DBR_PARAM_H_ 20 #define _WMI_UNIFIED_DBR_PARAM_H_ 21 22 #define WMI_HOST_DBR_RING_ADDR_LO_S 0 23 #define WMI_HOST_DBR_RING_ADDR_LO_M 0xffffffff 24 #define WMI_HOST_DBR_RING_ADDR_LO \ 25 (WMI_HOST_DBR_RING_ADDR_LO_M << WMI_HOST_DBR_RING_ADDR_LO_S) 26 27 #define WMI_HOST_DBR_RING_ADDR_LO_GET(dword) \ 28 WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_LO) 29 #define WMI_HOST_DBR_RING_ADDR_LO_SET(dword, val) \ 30 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_LO) 31 32 #define WMI_HOST_DBR_RING_ADDR_HI_S 0 33 #define WMI_HOST_DBR_RING_ADDR_HI_M 0xf 34 #define WMI_HOST_DBR_RING_ADDR_HI \ 35 (WMI_HOST_DBR_RING_ADDR_HI_M << WMI_HOST_DBR_RING_ADDR_HI_S) 36 37 #define WMI_HOST_DBR_RING_ADDR_HI_GET(dword) \ 38 WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_HI) 39 #define WMI_HOST_DBR_RING_ADDR_HI_SET(dword, val) \ 40 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_HI) 41 42 #define WMI_HOST_DBR_DATA_ADDR_LO_S 0 43 #define WMI_HOST_DBR_DATA_ADDR_LO_M 0xffffffff 44 #define WMI_HOST_DBR_DATA_ADDR_LO \ 45 (WMI_HOST_DBR_DATA_ADDR_LO_M << WMI_HOST_DBR_DATA_ADDR_LO_S) 46 47 #define WMI_HOST_DBR_DATA_ADDR_LO_GET(dword) \ 48 WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_LO) 49 #define WMI_HOST_DBR_DATA_ADDR_LO_SET(dword, val) \ 50 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_LO) 51 52 #define WMI_HOST_DBR_DATA_ADDR_HI_S 0 53 #define WMI_HOST_DBR_DATA_ADDR_HI_M 0xf 54 #define WMI_HOST_DBR_DATA_ADDR_HI \ 55 (WMI_HOST_DBR_DATA_ADDR_HI_M << WMI_HOST_DBR_DATA_ADDR_HI_S) 56 57 #define WMI_HOST_DBR_DATA_ADDR_HI_GET(dword) \ 58 WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI) 59 #define WMI_HOST_DBR_DATA_ADDR_HI_SET(dword, val) \ 60 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI) 61 62 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S 12 63 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M 0x7ffff 64 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA \ 65 (WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M << \ 66 WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S) 67 68 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_GET(dword) \ 69 WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA) 70 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_SET(dword, val) \ 71 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA) 72 73 #define WMI_HOST_MAX_NUM_CHAINS 8 74 75 /** 76 * struct direct_buf_rx_rsp: direct buffer rx response structure 77 * 78 * @pdev_id: Index of the pdev for which response is received 79 * @mod_mod: Index of the module for which respone is received 80 * @num_buf_release_entry: Number of buffers released through event 81 * @dbr_entries: Pointer to direct buffer rx entry struct 82 */ 83 struct direct_buf_rx_rsp { 84 uint32_t pdev_id; 85 uint32_t mod_id; 86 uint32_t num_buf_release_entry; 87 uint32_t num_meta_data_entry; 88 struct direct_buf_rx_entry *dbr_entries; 89 }; 90 91 /** 92 * struct direct_buf_rx_cfg_req: direct buffer rx config request structure 93 * 94 * @pdev_id: Index of the pdev for which response is received 95 * @mod_id: Index of the module for which respone is received 96 * @base_paddr_lo: Lower 32bits of ring base address 97 * @base_paddr_hi: Higher 32bits of ring base address 98 * @head_idx_paddr_lo: Lower 32bits of head idx register address 99 * @head_idx_paddr_hi: Higher 32bits of head idx register address 100 * @tail_idx_paddr_lo: Lower 32bits of tail idx register address 101 * @tail_idx_paddr_hi: Higher 32bits of tail idx register address 102 * @buf_size: Size of the buffer for each pointer in the ring 103 * @num_elems: Number of pointers allocated and part of the source ring 104 */ 105 struct direct_buf_rx_cfg_req { 106 uint32_t pdev_id; 107 uint32_t mod_id; 108 uint32_t base_paddr_lo; 109 uint32_t base_paddr_hi; 110 uint32_t head_idx_paddr_lo; 111 uint32_t head_idx_paddr_hi; 112 uint32_t tail_idx_paddr_hi; 113 uint32_t tail_idx_paddr_lo; 114 uint32_t buf_size; 115 uint32_t num_elems; 116 uint32_t event_timeout_ms; 117 uint32_t num_resp_per_event; 118 }; 119 120 /** 121 * struct direct_buf_rx_metadata: direct buffer metadata 122 * 123 * @noisefloor: noisefloor 124 * @reset_delay: reset delay 125 * @cfreq1: center frequency 1 126 * @cfreq2: center frequency 2 127 * @ch_width: channel width 128 */ 129 struct direct_buf_rx_metadata { 130 int32_t noisefloor[WMI_HOST_MAX_NUM_CHAINS]; 131 uint32_t reset_delay; 132 uint32_t cfreq1; 133 uint32_t cfreq2; 134 uint32_t ch_width; 135 }; 136 137 /** 138 * struct direct_buf_rx_entry: direct buffer rx release entry structure 139 * 140 * @addr_lo: LSB 32-bits of the buffer 141 * @addr_hi: MSB 32-bits of the buffer 142 * @len: Length of the buffer 143 */ 144 struct direct_buf_rx_entry { 145 uint32_t paddr_lo; 146 uint32_t paddr_hi; 147 uint32_t len; 148 }; 149 150 #endif /* _WMI_UNIFIED_DBR_PARAM_H_ */ 151