1 /* 2 * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _WMI_UNIFIED_DBR_PARAM_H_ 21 #define _WMI_UNIFIED_DBR_PARAM_H_ 22 23 #define WMI_HOST_DBR_RING_ADDR_LO_S 0 24 #define WMI_HOST_DBR_RING_ADDR_LO_M 0xffffffff 25 #define WMI_HOST_DBR_RING_ADDR_LO \ 26 (WMI_HOST_DBR_RING_ADDR_LO_M << WMI_HOST_DBR_RING_ADDR_LO_S) 27 28 #define WMI_HOST_DBR_RING_ADDR_LO_GET(dword) \ 29 WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_LO) 30 #define WMI_HOST_DBR_RING_ADDR_LO_SET(dword, val) \ 31 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_LO) 32 33 #define WMI_HOST_DBR_RING_ADDR_HI_S 0 34 #define WMI_HOST_DBR_RING_ADDR_HI_M 0xf 35 #define WMI_HOST_DBR_RING_ADDR_HI \ 36 (WMI_HOST_DBR_RING_ADDR_HI_M << WMI_HOST_DBR_RING_ADDR_HI_S) 37 38 #define WMI_HOST_DBR_RING_ADDR_HI_GET(dword) \ 39 WMI_HOST_F_MS(dword, WMI_HOST_DBR_RING_ADDR_HI) 40 #define WMI_HOST_DBR_RING_ADDR_HI_SET(dword, val) \ 41 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_RING_ADDR_HI) 42 43 #define WMI_HOST_DBR_DATA_ADDR_LO_S 0 44 #define WMI_HOST_DBR_DATA_ADDR_LO_M 0xffffffff 45 #define WMI_HOST_DBR_DATA_ADDR_LO \ 46 (WMI_HOST_DBR_DATA_ADDR_LO_M << WMI_HOST_DBR_DATA_ADDR_LO_S) 47 48 #define WMI_HOST_DBR_DATA_ADDR_LO_GET(dword) \ 49 WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_LO) 50 #define WMI_HOST_DBR_DATA_ADDR_LO_SET(dword, val) \ 51 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_LO) 52 53 #define WMI_HOST_DBR_DATA_ADDR_HI_S 0 54 #define WMI_HOST_DBR_DATA_ADDR_HI_M 0xf 55 #define WMI_HOST_DBR_DATA_ADDR_HI \ 56 (WMI_HOST_DBR_DATA_ADDR_HI_M << WMI_HOST_DBR_DATA_ADDR_HI_S) 57 58 #define WMI_HOST_DBR_DATA_ADDR_HI_GET(dword) \ 59 WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI) 60 #define WMI_HOST_DBR_DATA_ADDR_HI_SET(dword, val) \ 61 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI) 62 63 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S 12 64 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M 0x7ffff 65 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA \ 66 (WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_M << \ 67 WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_S) 68 69 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_GET(dword) \ 70 WMI_HOST_F_MS(dword, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA) 71 #define WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA_SET(dword, val) \ 72 WMI_HOST_F_RMW(dword, val, WMI_HOST_DBR_DATA_ADDR_HI_HOST_DATA) 73 74 #define WMI_HOST_MAX_NUM_CHAINS 8 75 76 /** 77 * struct direct_buf_rx_rsp: direct buffer rx response structure 78 * 79 * @pdev_id: Index of the pdev for which response is received 80 * @mod_id: Index of the module for which respone is received 81 * @num_buf_release_entry: Number of buffers released through event 82 * @num_meta_data_entry: 83 * @dbr_entries: Pointer to direct buffer rx entry struct 84 */ 85 struct direct_buf_rx_rsp { 86 uint32_t pdev_id; 87 uint32_t mod_id; 88 uint32_t num_buf_release_entry; 89 uint32_t num_meta_data_entry; 90 struct direct_buf_rx_entry *dbr_entries; 91 }; 92 93 /** 94 * struct direct_buf_rx_cfg_req: direct buffer rx config request structure 95 * 96 * @pdev_id: Index of the pdev for which response is received 97 * @mod_id: Index of the module for which respone is received 98 * @base_paddr_lo: Lower 32bits of ring base address 99 * @base_paddr_hi: Higher 32bits of ring base address 100 * @head_idx_paddr_lo: Lower 32bits of head idx register address 101 * @head_idx_paddr_hi: Higher 32bits of head idx register address 102 * @tail_idx_paddr_lo: Lower 32bits of tail idx register address 103 * @tail_idx_paddr_hi: Higher 32bits of tail idx register address 104 * @buf_size: Size of the buffer for each pointer in the ring 105 * @num_elems: Number of pointers allocated and part of the source ring 106 * @event_timeout_ms: 107 * @num_resp_per_event: 108 */ 109 struct direct_buf_rx_cfg_req { 110 uint32_t pdev_id; 111 uint32_t mod_id; 112 uint32_t base_paddr_lo; 113 uint32_t base_paddr_hi; 114 uint32_t head_idx_paddr_lo; 115 uint32_t head_idx_paddr_hi; 116 uint32_t tail_idx_paddr_hi; 117 uint32_t tail_idx_paddr_lo; 118 uint32_t buf_size; 119 uint32_t num_elems; 120 uint32_t event_timeout_ms; 121 uint32_t num_resp_per_event; 122 }; 123 124 /** 125 * struct direct_buf_rx_metadata: direct buffer metadata 126 * 127 * @noisefloor: noisefloor 128 * @reset_delay: reset delay 129 * @cfreq1: center frequency 1 130 * @cfreq2: center frequency 2 131 * @ch_width: channel width 132 */ 133 struct direct_buf_rx_metadata { 134 int32_t noisefloor[WMI_HOST_MAX_NUM_CHAINS]; 135 uint32_t reset_delay; 136 uint32_t cfreq1; 137 uint32_t cfreq2; 138 uint32_t ch_width; 139 }; 140 141 /** 142 * struct direct_buf_rx_entry: direct buffer rx release entry structure 143 * 144 * @paddr_lo: LSB 32-bits of the buffer 145 * @paddr_hi: MSB 32-bits of the buffer 146 * @len: Length of the buffer 147 */ 148 struct direct_buf_rx_entry { 149 uint32_t paddr_lo; 150 uint32_t paddr_hi; 151 uint32_t len; 152 }; 153 154 #endif /* _WMI_UNIFIED_DBR_PARAM_H_ */ 155