1 /* 2 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /** 20 * DOC: This file contains definitions of Data Path configuration. 21 */ 22 23 #ifndef _CFG_DP_H_ 24 #define _CFG_DP_H_ 25 26 #include "cfg_define.h" 27 28 #define WLAN_CFG_MAX_CLIENTS 64 29 #define WLAN_CFG_MAX_CLIENTS_MIN 8 30 #define WLAN_CFG_MAX_CLIENTS_MAX 64 31 32 /* Change this to a lower value to enforce scattered idle list mode */ 33 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 34 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 35 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 36 37 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 38 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 39 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 40 41 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 43 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 44 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 45 #else 46 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 47 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 48 #endif 49 50 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 51 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 52 53 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 54 #define WLAN_CFG_PER_PDEV_RX_RING 0 55 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 56 #define WLAN_LRO_ENABLE 0 57 #define WLAN_CFG_MAC_PER_TARGET 2 58 #ifdef IPA_OFFLOAD 59 /* Size of TCL TX Ring */ 60 #define WLAN_CFG_TX_RING_SIZE 1024 61 #define WLAN_CFG_PER_PDEV_TX_RING 0 62 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 63 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 64 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 65 #else 66 #define WLAN_CFG_TX_RING_SIZE 512 67 #define WLAN_CFG_PER_PDEV_TX_RING 1 68 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 69 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 70 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 71 #endif 72 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 73 74 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 75 #define WLAN_CFG_NUM_TX_DESC 1024 76 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 77 78 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 79 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 80 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 81 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 82 83 /* Interrupt Mitigation - Timer threshold in us */ 84 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 85 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 86 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 87 #endif 88 89 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 90 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 91 92 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 93 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 94 95 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 96 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 97 98 #define WLAN_CFG_TX_RING_SIZE_MIN 512 99 #define WLAN_CFG_TX_RING_SIZE_MAX 2048 100 101 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 102 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 103 104 #define WLAN_CFG_NUM_TX_DESC_MIN 1024 105 #define WLAN_CFG_NUM_TX_DESC_MAX 32768 106 107 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024 108 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 109 110 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 111 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 112 113 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1 114 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 115 116 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 117 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 118 119 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 120 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 121 122 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 123 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 124 125 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 126 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100 127 128 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 129 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 130 131 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 132 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 133 134 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 135 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 136 137 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 138 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 139 140 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 141 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 142 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 143 144 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 145 146 /* Per vdev pools */ 147 #define WLAN_CFG_NUM_TX_DESC_POOL 3 148 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 149 150 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 151 152 #ifdef TX_PER_PDEV_DESC_POOL 153 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 154 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 155 156 #else /* TX_PER_PDEV_DESC_POOL */ 157 158 #define WLAN_CFG_NUM_TX_DESC_POOL 3 159 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 160 161 #endif /* TX_PER_PDEV_DESC_POOL */ 162 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 163 164 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 165 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 166 167 #define WLAN_CFG_HTT_PKT_TYPE 2 168 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 169 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 170 171 #define WLAN_CFG_MAX_PEER_ID 64 172 #define WLAN_CFG_MAX_PEER_ID_MIN 64 173 #define WLAN_CFG_MAX_PEER_ID_MAX 64 174 175 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 176 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 177 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 178 179 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 180 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3 181 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3 182 183 #define WLAN_CFG_NUM_REO_DEST_RING 4 184 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 185 #define WLAN_CFG_NUM_REO_DEST_RING_MAX 4 186 187 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 64 188 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 189 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64 190 191 #define WLAN_CFG_TCL_CMD_RING_SIZE 32 192 #define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32 193 #define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32 194 195 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 196 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 197 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 198 199 #if defined(QCA_WIFI_QCA6290) 200 #define WLAN_CFG_REO_DST_RING_SIZE 1024 201 #else 202 #define WLAN_CFG_REO_DST_RING_SIZE 2048 203 #endif 204 205 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024 206 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048 207 208 #define WLAN_CFG_REO_REINJECT_RING_SIZE 32 209 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 210 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32 211 212 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 213 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 214 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 215 defined(QCA_WIFI_QCA6750) 216 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 217 #else 218 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 219 #endif 220 221 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128 222 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 223 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128 224 225 #define WLAN_CFG_REO_CMD_RING_SIZE 128 226 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 227 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 228 229 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 230 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 231 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 232 233 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 234 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 235 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024 236 237 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 238 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 239 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096 240 241 #define WLAN_CFG_TX_DESC_LIMIT_0 0 242 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 243 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 244 245 #define WLAN_CFG_TX_DESC_LIMIT_1 0 246 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 247 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 248 249 #define WLAN_CFG_TX_DESC_LIMIT_2 0 250 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 251 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 252 253 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 254 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 255 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 256 257 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 258 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 259 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 260 261 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 262 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 263 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 264 265 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 266 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 267 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 268 269 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 270 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 271 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 272 273 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 274 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 275 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 276 277 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 278 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 279 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 280 281 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 282 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 283 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 284 285 /** 286 * Allocate as many RX descriptors as buffers in the SW2RXDMA 287 * ring. This value may need to be tuned later. 288 */ 289 #if defined(QCA_HOST2FW_RXBUF_RING) 290 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 291 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 292 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 293 294 /** 295 * For low memory AP cases using 1 will reduce the rx descriptors memory req 296 */ 297 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 298 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 299 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 300 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 301 302 /** 303 * AP use cases need to allocate more RX Descriptors than the number of 304 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 305 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 306 * multiplication factor of 3, to allocate three times as many RX descriptors 307 * as RX buffers. 308 */ 309 #else 310 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 311 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 312 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 313 #endif //QCA_HOST2FW_RXBUF_RING 314 315 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 316 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 317 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 318 319 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 320 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 321 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 322 323 /* DP INI Declerations */ 324 #define CFG_DP_HTT_PACKET_TYPE \ 325 CFG_INI_UINT("dp_htt_packet_type", \ 326 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 327 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 328 WLAN_CFG_HTT_PKT_TYPE, \ 329 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 330 331 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 332 CFG_INI_UINT("dp_int_batch_threshold_other", \ 333 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 334 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 335 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 336 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 337 338 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 339 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 340 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 341 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 342 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 343 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 344 345 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 346 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 347 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 348 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 349 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 350 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 351 352 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 353 CFG_INI_UINT("dp_int_timer_threshold_other", \ 354 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 355 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 356 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 357 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 358 359 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 360 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 361 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 362 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 363 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 364 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 365 366 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 367 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 368 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 369 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 370 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 371 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 372 373 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 374 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 375 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 376 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 377 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 378 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 379 380 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 381 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 382 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 383 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 384 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 385 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 386 387 #define CFG_DP_MAX_ALLOC_SIZE \ 388 CFG_INI_UINT("dp_max_alloc_size", \ 389 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 390 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 391 WLAN_CFG_MAX_ALLOC_SIZE, \ 392 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 393 394 #define CFG_DP_MAX_CLIENTS \ 395 CFG_INI_UINT("dp_max_clients", \ 396 WLAN_CFG_MAX_CLIENTS_MIN, \ 397 WLAN_CFG_MAX_CLIENTS_MAX, \ 398 WLAN_CFG_MAX_CLIENTS, \ 399 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 400 401 #define CFG_DP_MAX_PEER_ID \ 402 CFG_INI_UINT("dp_max_peer_id", \ 403 WLAN_CFG_MAX_PEER_ID_MIN, \ 404 WLAN_CFG_MAX_PEER_ID_MAX, \ 405 WLAN_CFG_MAX_PEER_ID, \ 406 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 407 408 #define CFG_DP_REO_DEST_RINGS \ 409 CFG_INI_UINT("dp_reo_dest_rings", \ 410 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 411 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 412 WLAN_CFG_NUM_REO_DEST_RING, \ 413 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 414 415 #define CFG_DP_TCL_DATA_RINGS \ 416 CFG_INI_UINT("dp_tcl_data_rings", \ 417 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 418 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 419 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 420 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 421 422 #define CFG_DP_TX_DESC \ 423 CFG_INI_UINT("dp_tx_desc", \ 424 WLAN_CFG_NUM_TX_DESC_MIN, \ 425 WLAN_CFG_NUM_TX_DESC_MAX, \ 426 WLAN_CFG_NUM_TX_DESC, \ 427 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 428 429 #define CFG_DP_TX_EXT_DESC \ 430 CFG_INI_UINT("dp_tx_ext_desc", \ 431 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 432 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 433 WLAN_CFG_NUM_TX_EXT_DESC, \ 434 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 435 436 #define CFG_DP_TX_EXT_DESC_POOLS \ 437 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 438 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 439 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 440 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 441 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 442 443 #define CFG_DP_PDEV_RX_RING \ 444 CFG_INI_UINT("dp_pdev_rx_ring", \ 445 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 446 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 447 WLAN_CFG_PER_PDEV_RX_RING, \ 448 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 449 450 #define CFG_DP_PDEV_TX_RING \ 451 CFG_INI_UINT("dp_pdev_tx_ring", \ 452 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 453 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 454 WLAN_CFG_PER_PDEV_TX_RING, \ 455 CFG_VALUE_OR_DEFAULT, \ 456 "DP PDEV Tx Ring") 457 458 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 459 CFG_INI_UINT("dp_rx_defrag_timeout", \ 460 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 461 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 462 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 463 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 464 465 #define CFG_DP_TX_COMPL_RING_SIZE \ 466 CFG_INI_UINT("dp_tx_compl_ring_size", \ 467 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 468 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 469 WLAN_CFG_TX_COMP_RING_SIZE, \ 470 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 471 472 #define CFG_DP_TX_RING_SIZE \ 473 CFG_INI_UINT("dp_tx_ring_size", \ 474 WLAN_CFG_TX_RING_SIZE_MIN,\ 475 WLAN_CFG_TX_RING_SIZE_MAX,\ 476 WLAN_CFG_TX_RING_SIZE,\ 477 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 478 479 #define CFG_DP_NSS_COMP_RING_SIZE \ 480 CFG_INI_UINT("dp_nss_comp_ring_size", \ 481 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 482 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 483 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 484 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 485 486 #define CFG_DP_PDEV_LMAC_RING \ 487 CFG_INI_UINT("dp_pdev_lmac_ring", \ 488 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 489 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 490 WLAN_CFG_PER_PDEV_LMAC_RING, \ 491 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 492 493 #define CFG_DP_BASE_HW_MAC_ID \ 494 CFG_INI_UINT("dp_base_hw_macid", \ 495 0, 1, 1, \ 496 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 497 498 #define CFG_DP_RX_HASH \ 499 CFG_INI_BOOL("dp_rx_hash", true, \ 500 "DP Rx Hash") 501 502 #define CFG_DP_TSO \ 503 CFG_INI_BOOL("TSOEnable", false, \ 504 "DP TSO Enabled") 505 506 #define CFG_DP_LRO \ 507 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 508 "DP LRO Enable") 509 510 #define CFG_DP_SG \ 511 CFG_INI_BOOL("dp_sg_support", false, \ 512 "DP SG Enable") 513 514 #define CFG_DP_GRO \ 515 CFG_INI_BOOL("GROEnable", false, \ 516 "DP GRO Enable") 517 518 #define CFG_DP_OL_TX_CSUM \ 519 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 520 "DP tx csum Enable") 521 522 #define CFG_DP_OL_RX_CSUM \ 523 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 524 "DP rx csum Enable") 525 526 #define CFG_DP_RAWMODE \ 527 CFG_INI_BOOL("dp_rawmode_support", false, \ 528 "DP rawmode Enable") 529 530 #define CFG_DP_PEER_FLOW_CTRL \ 531 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 532 "DP peer flow ctrl Enable") 533 534 #define CFG_DP_NAPI \ 535 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 536 "DP Napi Enabled") 537 538 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 539 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 540 "DP TCP UDP Checksum Offload") 541 542 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 543 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 544 "DP Defrag Timeout Check") 545 546 #define CFG_DP_WBM_RELEASE_RING \ 547 CFG_INI_UINT("dp_wbm_release_ring", \ 548 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 549 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 550 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 551 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 552 553 #define CFG_DP_TCL_CMD_RING \ 554 CFG_INI_UINT("dp_tcl_cmd_ring", \ 555 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \ 556 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \ 557 WLAN_CFG_TCL_CMD_RING_SIZE, \ 558 CFG_VALUE_OR_DEFAULT, "DP TCL command ring") 559 560 #define CFG_DP_TCL_STATUS_RING \ 561 CFG_INI_UINT("dp_tcl_status_ring",\ 562 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 563 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 564 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 565 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 566 567 #define CFG_DP_REO_REINJECT_RING \ 568 CFG_INI_UINT("dp_reo_reinject_ring", \ 569 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 570 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 571 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 572 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 573 574 #define CFG_DP_RX_RELEASE_RING \ 575 CFG_INI_UINT("dp_rx_release_ring", \ 576 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 577 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 578 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 579 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 580 581 #define CFG_DP_REO_EXCEPTION_RING \ 582 CFG_INI_UINT("dp_reo_exception_ring", \ 583 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 584 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 585 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 586 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 587 588 #define CFG_DP_REO_CMD_RING \ 589 CFG_INI_UINT("dp_reo_cmd_ring", \ 590 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 591 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 592 WLAN_CFG_REO_CMD_RING_SIZE, \ 593 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 594 595 #define CFG_DP_REO_STATUS_RING \ 596 CFG_INI_UINT("dp_reo_status_ring", \ 597 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 598 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 599 WLAN_CFG_REO_STATUS_RING_SIZE, \ 600 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 601 602 #define CFG_DP_RXDMA_BUF_RING \ 603 CFG_INI_UINT("dp_rxdma_buf_ring", \ 604 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 605 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 606 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 607 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 608 609 #define CFG_DP_RXDMA_REFILL_RING \ 610 CFG_INI_UINT("dp_rxdma_refill_ring", \ 611 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 612 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 613 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 614 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 615 616 #define CFG_DP_TX_DESC_LIMIT_0 \ 617 CFG_INI_UINT("dp_tx_desc_limit_0", \ 618 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 619 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 620 WLAN_CFG_TX_DESC_LIMIT_0, \ 621 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 622 623 #define CFG_DP_TX_DESC_LIMIT_1 \ 624 CFG_INI_UINT("dp_tx_desc_limit_1", \ 625 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 626 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 627 WLAN_CFG_TX_DESC_LIMIT_1, \ 628 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 629 630 #define CFG_DP_TX_DESC_LIMIT_2 \ 631 CFG_INI_UINT("dp_tx_desc_limit_2", \ 632 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 633 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 634 WLAN_CFG_TX_DESC_LIMIT_2, \ 635 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 636 637 #define CFG_DP_TX_DEVICE_LIMIT \ 638 CFG_INI_UINT("dp_tx_device_limit", \ 639 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 640 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 641 WLAN_CFG_TX_DEVICE_LIMIT, \ 642 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 643 644 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 645 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 646 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 647 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 648 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 649 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 650 651 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 652 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 653 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 654 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 655 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 656 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 657 658 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 659 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 660 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 661 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 662 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 663 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 664 665 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 666 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 667 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 668 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 669 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 670 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 671 672 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 673 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 674 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 675 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 676 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 677 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 678 679 #define CFG_DP_RXDMA_ERR_DST_RING \ 680 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 681 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 682 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 683 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 684 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 685 686 #define CFG_DP_PER_PKT_LOGGING \ 687 CFG_INI_UINT("enable_verbose_debug", \ 688 0, 0xffff, 0, \ 689 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 690 691 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 692 CFG_INI_UINT("TxFlowStartQueueOffset", \ 693 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 694 CFG_VALUE_OR_DEFAULT, "Start queue offset") 695 696 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 697 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 698 0, 50, 15, \ 699 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 700 701 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 702 CFG_INI_UINT("IpaUcTxBufSize", \ 703 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 704 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 705 706 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 707 CFG_INI_UINT("IpaUcTxPartitionBase", \ 708 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 709 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 710 711 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 712 CFG_INI_UINT("IpaUcRxIndRingCount", \ 713 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 714 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 715 716 #define CFG_DP_REORDER_OFFLOAD_SUPPORT \ 717 CFG_INI_UINT("gReorderOffloadSupported", \ 718 0, 1, 1, \ 719 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware") 720 721 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 722 CFG_INI_BOOL("gDisableIntraBssFwd", \ 723 false, "Disable intrs BSS Rx packets") 724 725 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 726 CFG_INI_BOOL("gEnableDataStallDetection", \ 727 true, "Enable/Disable Data stall detection") 728 729 #define CFG_DP_RX_SW_DESC_WEIGHT \ 730 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 731 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 732 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 733 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 734 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 735 736 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 737 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 738 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 739 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 740 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE, \ 741 CFG_VALUE_OR_DEFAULT, \ 742 "DP Rx Flow Search Table Size in number of entries") 743 744 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 745 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 746 "Enable/Disable DP Rx Flow Tag") 747 748 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 749 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 750 "DP Rx Flow Search Table Is Per PDev") 751 752 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 753 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 754 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 755 756 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 757 CFG_INI_UINT("mon_drop_thresh", \ 758 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 759 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 760 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 761 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 762 763 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 764 CFG_INI_UINT("PktlogBufSize", \ 765 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 766 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 767 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 768 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 769 770 #define CFG_DP \ 771 CFG(CFG_DP_HTT_PACKET_TYPE) \ 772 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 773 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 774 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 775 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 776 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 777 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 778 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 779 CFG(CFG_DP_MAX_CLIENTS) \ 780 CFG(CFG_DP_MAX_PEER_ID) \ 781 CFG(CFG_DP_REO_DEST_RINGS) \ 782 CFG(CFG_DP_TCL_DATA_RINGS) \ 783 CFG(CFG_DP_TX_DESC) \ 784 CFG(CFG_DP_TX_EXT_DESC) \ 785 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 786 CFG(CFG_DP_PDEV_RX_RING) \ 787 CFG(CFG_DP_PDEV_TX_RING) \ 788 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 789 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 790 CFG(CFG_DP_TX_RING_SIZE) \ 791 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 792 CFG(CFG_DP_PDEV_LMAC_RING) \ 793 CFG(CFG_DP_BASE_HW_MAC_ID) \ 794 CFG(CFG_DP_RX_HASH) \ 795 CFG(CFG_DP_TSO) \ 796 CFG(CFG_DP_LRO) \ 797 CFG(CFG_DP_SG) \ 798 CFG(CFG_DP_GRO) \ 799 CFG(CFG_DP_OL_TX_CSUM) \ 800 CFG(CFG_DP_OL_RX_CSUM) \ 801 CFG(CFG_DP_RAWMODE) \ 802 CFG(CFG_DP_PEER_FLOW_CTRL) \ 803 CFG(CFG_DP_NAPI) \ 804 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 805 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 806 CFG(CFG_DP_WBM_RELEASE_RING) \ 807 CFG(CFG_DP_TCL_CMD_RING) \ 808 CFG(CFG_DP_TCL_STATUS_RING) \ 809 CFG(CFG_DP_REO_REINJECT_RING) \ 810 CFG(CFG_DP_RX_RELEASE_RING) \ 811 CFG(CFG_DP_REO_EXCEPTION_RING) \ 812 CFG(CFG_DP_REO_CMD_RING) \ 813 CFG(CFG_DP_REO_STATUS_RING) \ 814 CFG(CFG_DP_RXDMA_BUF_RING) \ 815 CFG(CFG_DP_RXDMA_REFILL_RING) \ 816 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 817 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 818 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 819 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 820 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 821 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 822 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 823 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 824 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 825 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 826 CFG(CFG_DP_PER_PKT_LOGGING) \ 827 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 828 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 829 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 830 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 831 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 832 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \ 833 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 834 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 835 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 836 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 837 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 838 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 839 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 840 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 841 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) 842 843 #endif /* _CFG_DP_H_ */ 844