1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #ifdef IPA_OFFLOAD 52 /* Size of TCL TX Ring */ 53 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 54 #define WLAN_CFG_TX_RING_SIZE 2048 55 #else 56 #define WLAN_CFG_TX_RING_SIZE 1024 57 #endif 58 59 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 512 60 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 61 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 0x80000 62 63 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 512 64 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 65 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 0x80000 66 67 #ifdef IPA_WDI3_TX_TWO_PIPES 68 #ifdef WLAN_MEMORY_OPT 69 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 128 70 #else 71 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 512 72 #endif 73 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 0x80000 75 76 #ifdef WLAN_MEMORY_OPT 77 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 128 78 #else 79 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 512 80 #endif 81 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 82 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 0x80000 83 #endif 84 85 #define WLAN_CFG_PER_PDEV_TX_RING 0 86 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 87 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 88 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 89 #else 90 #define WLAN_CFG_TX_RING_SIZE 512 91 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 92 #define WLAN_CFG_PER_PDEV_TX_RING 1 93 #else 94 #define WLAN_CFG_PER_PDEV_TX_RING 0 95 #endif 96 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 97 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 98 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 99 #endif /* IPA_OFFLOAD */ 100 101 #define WLAN_CFG_TIME_CONTROL_BP 3000 102 103 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 104 #define WLAN_CFG_PER_PDEV_RX_RING 0 105 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 106 #define WLAN_LRO_ENABLE 0 107 #if defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_WCN6450) 108 #define WLAN_CFG_MAC_PER_TARGET 1 109 #else 110 #define WLAN_CFG_MAC_PER_TARGET 2 111 #endif 112 113 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 114 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 115 116 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 117 #define WLAN_CFG_NUM_TX_DESC 4096 118 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 119 #else 120 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 121 122 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 123 #define WLAN_CFG_NUM_TX_DESC 1024 124 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 125 #endif 126 127 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 128 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 129 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 130 131 /* Interrupt Mitigation - Timer threshold in us */ 132 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 133 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 134 135 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 136 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 137 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 138 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 139 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 140 #else 141 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 142 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 143 #endif 144 #endif /* WLAN_MAX_PDEVS */ 145 146 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL 0 147 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL 30 148 149 #ifdef NBUF_MEMORY_DEBUG 150 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 151 #else 152 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 153 #endif 154 155 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 156 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 157 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 158 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 159 160 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 161 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 162 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 163 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 164 165 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 166 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 167 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 168 169 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 170 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 171 172 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 173 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 174 175 #define WLAN_CFG_TX_RING_SIZE_MIN 512 176 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 177 178 #define WLAN_CFG_TIME_CONTROL_BP_MIN 3000 179 #define WLAN_CFG_TIME_CONTROL_BP_MAX 1800000 180 181 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 182 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 183 184 #define WLAN_CFG_NUM_TX_DESC_MIN 16 185 #define WLAN_CFG_NUM_TX_DESC_MAX 0x10000 186 187 #define WLAN_CFG_NUM_TX_SPL_DESC 1024 188 #define WLAN_CFG_NUM_TX_SPL_DESC_MIN 0 189 #define WLAN_CFG_NUM_TX_SPL_DESC_MAX 0x1000 190 191 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 192 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 193 194 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 195 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 196 197 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN 0 198 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX 1024 199 200 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 201 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 202 203 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 204 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 205 206 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 207 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 208 209 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 210 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 211 212 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 213 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 214 215 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN 8 216 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX 1000 217 218 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 219 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 220 221 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 222 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 223 224 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 225 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 226 227 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 228 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 229 230 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 231 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 232 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 233 234 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 235 236 /* Per vdev pools */ 237 #define WLAN_CFG_NUM_TX_DESC_POOL 3 238 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 239 240 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 241 242 #ifdef TX_PER_PDEV_DESC_POOL 243 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 244 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 245 246 #else /* TX_PER_PDEV_DESC_POOL */ 247 248 #define WLAN_CFG_NUM_TX_DESC_POOL 3 249 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 250 251 #endif /* TX_PER_PDEV_DESC_POOL */ 252 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 253 254 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 255 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 256 257 #define WLAN_CFG_HTT_PKT_TYPE 2 258 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 259 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 260 261 #define WLAN_CFG_MAX_PEER_ID 64 262 #define WLAN_CFG_MAX_PEER_ID_MIN 64 263 #define WLAN_CFG_MAX_PEER_ID_MAX 64 264 265 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 266 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 267 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 268 269 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 270 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 271 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 272 273 #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 274 #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 275 #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 276 277 #if defined(CONFIG_BERYLLIUM) 278 #define WLAN_CFG_NUM_REO_DEST_RING 8 279 #else 280 #define WLAN_CFG_NUM_REO_DEST_RING 4 281 #endif 282 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 283 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 284 285 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 286 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 287 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 288 289 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 290 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 291 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 292 293 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 294 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 295 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 296 297 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 298 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 299 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 300 301 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 302 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 303 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 304 305 #if defined(QCA_WIFI_QCA6290) 306 #define WLAN_CFG_REO_DST_RING_SIZE 1024 307 #else 308 #define WLAN_CFG_REO_DST_RING_SIZE 2048 309 #endif 310 311 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 312 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 313 314 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 315 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 316 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 317 318 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 319 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 320 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 321 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 322 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 323 #else 324 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 32768 325 #endif 326 327 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 328 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 329 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 330 331 #define WLAN_CFG_REO_CMD_RING_SIZE 128 332 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 333 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 334 335 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 336 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 337 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 338 339 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 340 #ifdef WLAN_MEMORY_OPT 341 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 128 342 #else 343 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 344 #endif 345 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 4096 346 347 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 348 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 349 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 16384 350 351 #define WLAN_CFG_TX_DESC_LIMIT_0 0 352 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 353 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 354 355 #define WLAN_CFG_TX_DESC_LIMIT_1 0 356 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 357 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 358 359 #define WLAN_CFG_TX_DESC_LIMIT_2 0 360 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 361 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 362 363 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 364 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 365 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 366 367 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT 1024 368 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN 0 369 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX 4096 370 371 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 372 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 373 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 374 375 #define WLAN_CFG_TX_DESC_GLOBAL_COUNT 0xC000 376 #define WLAN_CFG_TX_DESC_GLOBAL_COUNT_MIN 0x8000 377 #define WLAN_CFG_TX_DESC_GLOBAL_COUNT_MAX 0x60000 378 379 #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT 0x400 380 #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MIN 0x400 381 #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MAX 0x1000 382 383 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 384 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 385 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 386 387 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 388 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 389 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 390 391 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 392 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 393 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 394 395 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 396 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 397 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 8192 398 399 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 400 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 401 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 402 403 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 404 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 405 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 406 407 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 408 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 409 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 410 411 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 412 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 413 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 414 415 /* 416 * Allocate as many RX descriptors as buffers in the SW2RXDMA 417 * ring. This value may need to be tuned later. 418 */ 419 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 420 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 421 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 422 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 423 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 424 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 425 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 426 427 /* 428 * For low memory AP cases using 1 will reduce the rx descriptors memory req 429 */ 430 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 431 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 432 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 433 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 434 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 435 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 436 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 437 438 /* 439 * AP use cases need to allocate more RX Descriptors than the number of 440 * entries available in the SW2RXDMA buffer replenish ring. This is to account 441 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 442 * multiplication factor of 3, to allocate three times as many RX descriptors 443 * as RX buffers. 444 */ 445 #else 446 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 447 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 448 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 449 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 450 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 451 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 452 #endif 453 454 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 455 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 456 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 457 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 458 459 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 460 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 461 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 462 463 #ifdef IPA_OFFLOAD 464 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 465 #else 466 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 467 #endif 468 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 469 #if defined(CONFIG_BERYLLIUM) 470 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xFF 471 #else 472 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 473 #endif 474 475 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 476 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 477 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 478 479 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 480 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 481 482 #define WLAN_CFG_REO2PPE_RING_SIZE 8192 483 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 484 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 16384 485 486 #define WLAN_CFG_PPE2TCL_RING_SIZE 2048 487 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 488 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 32768 489 490 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 491 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 492 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 493 494 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 495 #define WLAN_CFG_MLO_RX_RING_MAP 0x7 496 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 497 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 498 #endif 499 500 #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 501 #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 502 #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 503 504 #define CFG_DP_MPDU_RETRY_THRESHOLD_MIN 0 505 #define CFG_DP_MPDU_RETRY_THRESHOLD_MAX 255 506 #define CFG_DP_MPDU_RETRY_THRESHOLD 0 507 508 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR 0 509 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN 0 510 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX 4 511 512 #define CFG_DP_PPEDS_WIFI_SOC_CFG_NONE 0 513 #define CFG_DP_PPEDS_WIFI_SOC_CFG_ALL 0xFF 514 #define CFG_DP_PPEDS_WIFI_SOC_CFG_DEFAULT 0xFF 515 516 #ifdef CONFIG_SAWF_STATS 517 #define WLAN_CFG_SAWF_STATS 0x0 518 #define WLAN_CFG_SAWF_STATS_MIN 0x0 519 #define WLAN_CFG_SAWF_STATS_MAX 0x7 520 #endif 521 /* 522 * <ini> 523 * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 524 * @Min: 0 525 * @Max: 512 MB 526 * @Default: 0 (disabled) 527 * 528 * This ini entry is used to set a max limit beyond which frames 529 * are dropped by Tx capture. User needs to set a non-zero value 530 * to enable it. 531 * 532 * Usage: External 533 * 534 * </ini> 535 */ 536 #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 537 CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 538 WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 539 WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 540 WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 541 CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 542 543 /* DP INI Declarations */ 544 #define CFG_DP_HTT_PACKET_TYPE \ 545 CFG_INI_UINT("dp_htt_packet_type", \ 546 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 547 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 548 WLAN_CFG_HTT_PKT_TYPE, \ 549 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 550 551 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 552 CFG_INI_UINT("dp_int_batch_threshold_other", \ 553 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 554 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 555 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 556 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 557 558 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 559 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 560 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 561 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 562 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 563 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 564 565 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 566 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 567 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 568 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 569 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 570 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 571 572 #define CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL \ 573 CFG_INI_UINT("dp_int_batch_threshold_ppe2tcl", \ 574 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN, \ 575 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX, \ 576 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL, \ 577 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold ppe2tcl") 578 579 #define CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL \ 580 CFG_INI_UINT("dp_int_timer_threshold_ppe2tcl", \ 581 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN, \ 582 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX, \ 583 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL, \ 584 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold ppe2tcl") 585 586 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 587 CFG_INI_UINT("dp_int_timer_threshold_other", \ 588 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 589 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 590 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 591 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 592 593 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 594 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 595 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 596 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 597 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 598 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 599 600 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 601 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 602 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 603 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 604 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 605 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 606 607 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 608 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 609 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 610 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 611 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 612 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 613 614 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 615 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 616 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 617 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 618 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 619 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 620 621 #define CFG_DP_MAX_ALLOC_SIZE \ 622 CFG_INI_UINT("dp_max_alloc_size", \ 623 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 624 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 625 WLAN_CFG_MAX_ALLOC_SIZE, \ 626 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 627 628 #define CFG_DP_MAX_CLIENTS \ 629 CFG_INI_UINT("dp_max_clients", \ 630 WLAN_CFG_MAX_CLIENTS_MIN, \ 631 WLAN_CFG_MAX_CLIENTS_MAX, \ 632 WLAN_CFG_MAX_CLIENTS, \ 633 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 634 635 #define CFG_DP_MAX_PEER_ID \ 636 CFG_INI_UINT("dp_max_peer_id", \ 637 WLAN_CFG_MAX_PEER_ID_MIN, \ 638 WLAN_CFG_MAX_PEER_ID_MAX, \ 639 WLAN_CFG_MAX_PEER_ID, \ 640 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 641 642 #define CFG_DP_REO_DEST_RINGS \ 643 CFG_INI_UINT("dp_reo_dest_rings", \ 644 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 645 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 646 WLAN_CFG_NUM_REO_DEST_RING, \ 647 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 648 649 #define CFG_DP_TX_COMP_RINGS \ 650 CFG_INI_UINT("dp_tx_comp_rings", \ 651 WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 652 WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 653 WLAN_CFG_NUM_TX_COMP_RINGS, \ 654 CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 655 656 #define CFG_DP_TCL_DATA_RINGS \ 657 CFG_INI_UINT("dp_tcl_data_rings", \ 658 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 659 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 660 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 661 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 662 663 #define CFG_DP_NSS_REO_DEST_RINGS \ 664 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 665 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 666 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 667 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 668 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 669 670 #define CFG_DP_NSS_TCL_DATA_RINGS \ 671 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 672 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 673 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 674 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 675 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 676 677 #define CFG_DP_TX_DESC \ 678 CFG_INI_UINT("dp_tx_desc", \ 679 WLAN_CFG_NUM_TX_DESC_MIN, \ 680 WLAN_CFG_NUM_TX_DESC_MAX, \ 681 WLAN_CFG_NUM_TX_DESC, \ 682 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 683 684 #define CFG_DP_TX_SPL_DESC \ 685 CFG_INI_UINT("dp_tx_spl_desc", \ 686 WLAN_CFG_NUM_TX_SPL_DESC_MIN, \ 687 WLAN_CFG_NUM_TX_SPL_DESC_MAX, \ 688 WLAN_CFG_NUM_TX_SPL_DESC, \ 689 CFG_VALUE_OR_DEFAULT, "DP Tx Special Descriptors") 690 691 #define CFG_DP_TX_EXT_DESC \ 692 CFG_INI_UINT("dp_tx_ext_desc", \ 693 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 694 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 695 WLAN_CFG_NUM_TX_EXT_DESC, \ 696 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 697 698 #define CFG_DP_TX_EXT_DESC_POOLS \ 699 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 700 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 701 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 702 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 703 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 704 705 #define CFG_DP_PDEV_RX_RING \ 706 CFG_INI_UINT("dp_pdev_rx_ring", \ 707 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 708 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 709 WLAN_CFG_PER_PDEV_RX_RING, \ 710 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 711 712 #define CFG_DP_PDEV_TX_RING \ 713 CFG_INI_UINT("dp_pdev_tx_ring", \ 714 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 715 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 716 WLAN_CFG_PER_PDEV_TX_RING, \ 717 CFG_VALUE_OR_DEFAULT, \ 718 "DP PDEV Tx Ring") 719 720 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 721 CFG_INI_UINT("dp_rx_defrag_timeout", \ 722 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 723 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 724 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 725 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 726 727 #define CFG_DP_TX_COMPL_RING_SIZE \ 728 CFG_INI_UINT("dp_tx_compl_ring_size", \ 729 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 730 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 731 WLAN_CFG_TX_COMP_RING_SIZE, \ 732 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 733 734 #define CFG_DP_TX_RING_SIZE \ 735 CFG_INI_UINT("dp_tx_ring_size", \ 736 WLAN_CFG_TX_RING_SIZE_MIN,\ 737 WLAN_CFG_TX_RING_SIZE_MAX,\ 738 WLAN_CFG_TX_RING_SIZE,\ 739 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 740 741 #define CFG_DP_NSS_COMP_RING_SIZE \ 742 CFG_INI_UINT("dp_nss_comp_ring_size", \ 743 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 744 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 745 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 746 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 747 748 #define CFG_DP_PDEV_LMAC_RING \ 749 CFG_INI_UINT("dp_pdev_lmac_ring", \ 750 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 751 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 752 WLAN_CFG_PER_PDEV_LMAC_RING, \ 753 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 754 755 #define CFG_DP_TIME_CONTROL_BP \ 756 CFG_INI_UINT("dp_time_control_bp", \ 757 WLAN_CFG_TIME_CONTROL_BP_MIN,\ 758 WLAN_CFG_TIME_CONTROL_BP_MAX,\ 759 WLAN_CFG_TIME_CONTROL_BP,\ 760 CFG_VALUE_OR_DEFAULT, "DP time control back pressure") 761 762 #ifdef CONFIG_SAWF_STATS 763 #define CFG_DP_SAWF_STATS \ 764 CFG_INI_UINT("dp_sawf_stats", \ 765 WLAN_CFG_SAWF_STATS_MIN,\ 766 WLAN_CFG_SAWF_STATS_MAX,\ 767 WLAN_CFG_SAWF_STATS,\ 768 CFG_VALUE_OR_DEFAULT, "DP sawf stats config") 769 #define CFG_DP_SAWF_STATS_CONFIG CFG(CFG_DP_SAWF_STATS) 770 #else 771 #define CFG_DP_SAWF_STATS_CONFIG 772 #endif 773 774 /* 775 * <ini> 776 * dp_rx_pending_hl_threshold - High threshold of frame number to start 777 * frame dropping scheme 778 * @Min: 0 779 * @Max: 524288 780 * @Default: 393216 781 * 782 * This ini entry is used to set a high limit threshold to start frame 783 * dropping scheme 784 * 785 * Usage: External 786 * 787 * </ini> 788 */ 789 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 790 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 791 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 792 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 793 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 794 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 795 796 /* 797 * <ini> 798 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 799 * frame dropping scheme 800 * @Min: 100 801 * @Max: 524288 802 * @Default: 393216 803 * 804 * This ini entry is used to set a low limit threshold to stop frame 805 * dropping scheme 806 * 807 * Usage: External 808 * 809 * </ini> 810 */ 811 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 812 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 813 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 814 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 815 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 816 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 817 818 #define CFG_DP_BASE_HW_MAC_ID \ 819 CFG_INI_UINT("dp_base_hw_macid", \ 820 0, 1, 1, \ 821 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 822 823 #define CFG_DP_RX_HASH \ 824 CFG_INI_BOOL("dp_rx_hash", true, \ 825 "DP Rx Hash") 826 827 #define CFG_DP_TSO \ 828 CFG_INI_BOOL("TSOEnable", false, \ 829 "DP TSO Enabled") 830 831 #define CFG_DP_LRO \ 832 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 833 "DP LRO Enable") 834 835 #ifdef WLAN_USE_CONFIG_PARAMS 836 /* 837 * <ini> 838 * dp_tx_desc_use_512p - Use 512M tx descriptor size 839 * @Min: 0 840 * @Max: 1 841 * @Default: 0 842 * 843 * This ini entry is used as flag to use 512M tx descriptor size or not 844 * 845 * Usage: Internal 846 * 847 * </ini> 848 */ 849 #define CFG_DP_TX_DESC_512P \ 850 CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 851 "DP TX DESC PINE SPECIFIC") 852 853 /* 854 * <ini> 855 * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 856 * @Min: 0 857 * @Max: 1 858 * @Default: 0 859 * 860 * This ini entry is used as flag to use 3 Radio NSS com ring size or not 861 * 862 * Usage: Internal 863 * 864 * </ini> 865 */ 866 #define CFG_DP_NSS_3RADIO_RING \ 867 CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 868 "DP NSS 3 RADIO RING SIZE") 869 870 /* 871 * <ini> 872 * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 873 * @Min: 0 874 * @Max: 1 875 * @Default: 0 876 * 877 * This ini entry is used as flag to update monitor status ring as 512M profile 878 * 879 * Usage: Internal 880 * 881 * </ini> 882 */ 883 #define CFG_DP_MON_STATUS_512M \ 884 CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 885 "DP MON STATUS RING SIZE PER 512M PROFILE") 886 887 /* 888 * <ini> 889 * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 890 * @Min: 0 891 * @Max: 1 892 * @Default: 0 893 * 894 * This ini entry is used as flag to reduce monitor rings size as those used 895 * in case of 2 Tx/RxChains 896 * 897 * Usage: Internal 898 * 899 * </ini> 900 */ 901 #define CFG_DP_MON_2CHAIN_RING \ 902 CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 903 "DP MON UPDATE RINGS FOR 2CHAIN") 904 905 /* 906 * <ini> 907 * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 908 * @Min: 0 909 * @Max: 1 910 * @Default: 0 911 * 912 * This ini entry is used as flag to reduce monitor rings size as those used 913 * in case of 4 Tx/RxChains 914 * 915 * Usage: Internal 916 * 917 * </ini> 918 */ 919 #define CFG_DP_MON_4CHAIN_RING \ 920 CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 921 "DP MON UPDATE RINGS FOR 4CHAIN") 922 923 /* 924 * <ini> 925 * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 926 * @Min: 0 927 * @Max: 1 928 * @Default: 0 929 * 930 * This ini entry is used as flag to update RDP reo map based on 4 Radio config 931 * 932 * Usage: Internal 933 * 934 * </ini> 935 */ 936 #define CFG_DP_4RADIO_RDP_REO \ 937 CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 938 false, "Update REO destination mapping for 4radio") 939 940 #define CFG_DP_INI_SECTION_PARAMS \ 941 CFG(CFG_DP_NSS_3RADIO_RING) \ 942 CFG(CFG_DP_TX_DESC_512P) \ 943 CFG(CFG_DP_MON_STATUS_512M) \ 944 CFG(CFG_DP_MON_2CHAIN_RING) \ 945 CFG(CFG_DP_MON_4CHAIN_RING) \ 946 CFG(CFG_DP_4RADIO_RDP_REO) 947 #else 948 #define CFG_DP_INI_SECTION_PARAMS 949 #endif 950 951 /* 952 * <ini> 953 * CFG_DP_SG - Enable the SG feature standalonely 954 * @Min: 0 955 * @Max: 1 956 * @Default: 1 957 * 958 * This ini entry is used to enable/disable SG feature standalonely. 959 * Also does Rome support SG on TX, lithium does not. 960 * For example the lithium does not support SG on UDP frames. 961 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 962 * 963 * Usage: External 964 * 965 * </ini> 966 */ 967 #define CFG_DP_SG \ 968 CFG_INI_BOOL("dp_sg_support", false, \ 969 "DP SG Enable") 970 971 #define WLAN_CFG_GRO_ENABLE_MIN 0 972 #define WLAN_CFG_GRO_ENABLE_MAX 3 973 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 974 #define DP_GRO_ENABLE_BIT_SET BIT(0) 975 #define DP_TC_BASED_DYNAMIC_GRO BIT(1) 976 977 /* 978 * <ini> 979 * CFG_DP_GRO - Enable the GRO feature standalonely 980 * @Min: 0 981 * @Max: 3 982 * @Default: 0 983 * 984 * This ini entry is used to enable/disable GRO feature standalonely. 985 * Value 0: Disable GRO feature 986 * Value 1: Enable GRO feature always 987 * Value 3: Enable GRO dynamic feature where TC rule can control GRO 988 * behavior 989 * 990 * Usage: External 991 * 992 * </ini> 993 */ 994 #define CFG_DP_GRO \ 995 CFG_INI_UINT("GROEnable", \ 996 WLAN_CFG_GRO_ENABLE_MIN, \ 997 WLAN_CFG_GRO_ENABLE_MAX, \ 998 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 999 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 1000 1001 #define WLAN_CFG_TC_INGRESS_PRIO_MIN 0 1002 #define WLAN_CFG_TC_INGRESS_PRIO_MAX 0xFFFF 1003 #define WLAN_CFG_TC_INGRESS_PRIO_DEFAULT 0 1004 1005 #define CFG_DP_TC_INGRESS_PRIO \ 1006 CFG_INI_UINT("tc_ingress_prio", \ 1007 WLAN_CFG_TC_INGRESS_PRIO_MIN, \ 1008 WLAN_CFG_TC_INGRESS_PRIO_MAX, \ 1009 WLAN_CFG_TC_INGRESS_PRIO_DEFAULT, \ 1010 CFG_VALUE_OR_DEFAULT, "DP tc ingress prio") 1011 1012 #define CFG_DP_OL_TX_CSUM \ 1013 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 1014 "DP tx csum Enable") 1015 1016 #define CFG_DP_OL_RX_CSUM \ 1017 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 1018 "DP rx csum Enable") 1019 1020 #define CFG_DP_RAWMODE \ 1021 CFG_INI_BOOL("dp_rawmode_support", false, \ 1022 "DP rawmode Enable") 1023 1024 #define CFG_DP_PEER_FLOW_CTRL \ 1025 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 1026 "DP peer flow ctrl Enable") 1027 1028 #define CFG_DP_NAPI \ 1029 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 1030 "DP Napi Enabled") 1031 /* 1032 * <ini> 1033 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 1034 * @Min: 0 1035 * @Max: 1 1036 * @Default: 1 1037 * 1038 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 1039 * This includes P2P device mode, P2P client mode and P2P GO mode. 1040 * The feature is enabled by default. To disable TX checksum for P2P, add the 1041 * following entry in ini file: 1042 * gEnableP2pIpTcpUdpChecksumOffload=0 1043 * 1044 * Usage: External 1045 * 1046 * </ini> 1047 */ 1048 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 1049 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 1050 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 1051 1052 /* 1053 * <ini> 1054 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 1055 * @Min: 0 1056 * @Max: 1 1057 * @Default: 1 1058 * 1059 * Usage: External 1060 * 1061 * </ini> 1062 */ 1063 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 1064 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 1065 "DP TCP UDP Checksum Offload for NAN mode") 1066 1067 /* 1068 * <ini> 1069 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 1070 * @Min: 0 1071 * @Max: 1 1072 * @Default: 1 1073 * 1074 * Usage: External 1075 * 1076 * </ini> 1077 */ 1078 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 1079 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 1080 "DP TCP UDP Checksum Offload") 1081 1082 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 1083 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 1084 "DP Defrag Timeout Check") 1085 1086 #define CFG_DP_WBM_RELEASE_RING \ 1087 CFG_INI_UINT("dp_wbm_release_ring", \ 1088 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 1089 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 1090 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 1091 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 1092 1093 #define CFG_DP_TCL_CMD_CREDIT_RING \ 1094 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 1095 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 1096 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 1097 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 1098 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 1099 1100 #define CFG_DP_TCL_STATUS_RING \ 1101 CFG_INI_UINT("dp_tcl_status_ring",\ 1102 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 1103 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 1104 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 1105 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 1106 1107 #define CFG_DP_REO_REINJECT_RING \ 1108 CFG_INI_UINT("dp_reo_reinject_ring", \ 1109 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 1110 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 1111 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1112 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1113 1114 #define CFG_DP_RX_RELEASE_RING \ 1115 CFG_INI_UINT("dp_rx_release_ring", \ 1116 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1117 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1118 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1119 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1120 1121 #define CFG_DP_RX_DESTINATION_RING \ 1122 CFG_INI_UINT("dp_reo_dst_ring", \ 1123 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 1124 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 1125 WLAN_CFG_REO_DST_RING_SIZE, \ 1126 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 1127 1128 #define CFG_DP_REO_EXCEPTION_RING \ 1129 CFG_INI_UINT("dp_reo_exception_ring", \ 1130 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1131 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1132 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1133 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1134 1135 #define CFG_DP_REO_CMD_RING \ 1136 CFG_INI_UINT("dp_reo_cmd_ring", \ 1137 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1138 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1139 WLAN_CFG_REO_CMD_RING_SIZE, \ 1140 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1141 1142 #define CFG_DP_REO_STATUS_RING \ 1143 CFG_INI_UINT("dp_reo_status_ring", \ 1144 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1145 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1146 WLAN_CFG_REO_STATUS_RING_SIZE, \ 1147 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1148 1149 #define CFG_DP_RXDMA_BUF_RING \ 1150 CFG_INI_UINT("dp_rxdma_buf_ring", \ 1151 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1152 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1153 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1154 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1155 1156 #define CFG_DP_RXDMA_REFILL_RING \ 1157 CFG_INI_UINT("dp_rxdma_refill_ring", \ 1158 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1159 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1160 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1161 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1162 1163 #define CFG_DP_RXDMA_REFILL_LT_DISABLE \ 1164 CFG_INI_BOOL("dp_disable_rx_buf_low_threshold", false, \ 1165 "Disable Low threshold interrupts for Rx Refill ring") 1166 1167 #define CFG_DP_TX_DESC_LIMIT_0 \ 1168 CFG_INI_UINT("dp_tx_desc_limit_0", \ 1169 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 1170 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 1171 WLAN_CFG_TX_DESC_LIMIT_0, \ 1172 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 1173 1174 #define CFG_DP_TX_DESC_LIMIT_1 \ 1175 CFG_INI_UINT("dp_tx_desc_limit_1", \ 1176 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 1177 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 1178 WLAN_CFG_TX_DESC_LIMIT_1, \ 1179 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 1180 1181 #define CFG_DP_TX_DESC_LIMIT_2 \ 1182 CFG_INI_UINT("dp_tx_desc_limit_2", \ 1183 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 1184 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 1185 WLAN_CFG_TX_DESC_LIMIT_2, \ 1186 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 1187 1188 #define CFG_DP_TX_DEVICE_LIMIT \ 1189 CFG_INI_UINT("dp_tx_device_limit", \ 1190 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1191 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1192 WLAN_CFG_TX_DEVICE_LIMIT, \ 1193 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1194 1195 #define CFG_DP_TX_SPL_DEVICE_LIMIT \ 1196 CFG_INI_UINT("dp_tx_spl_device_limit", \ 1197 WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN, \ 1198 WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX, \ 1199 WLAN_CFG_TX_SPL_DEVICE_LIMIT, \ 1200 CFG_VALUE_OR_DEFAULT, "DP TX Special DEVICE limit") 1201 1202 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1203 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1204 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1205 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1206 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1207 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1208 1209 #define CFG_DP_TX_DESC_GLOBAL_COUNT \ 1210 CFG_INI_UINT("dp_tx_desc_global", \ 1211 WLAN_CFG_TX_DESC_GLOBAL_COUNT_MIN, \ 1212 WLAN_CFG_TX_DESC_GLOBAL_COUNT_MAX, \ 1213 WLAN_CFG_TX_DESC_GLOBAL_COUNT, \ 1214 CFG_VALUE_OR_DEFAULT, "DP Global TX descriptor count") 1215 1216 #define CFG_DP_SPCL_TX_DESC_GLOBAL_COUNT \ 1217 CFG_INI_UINT("dp_spcl_tx_desc_global", \ 1218 WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MIN, \ 1219 WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MAX, \ 1220 WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT, \ 1221 CFG_VALUE_OR_DEFAULT, "DP Global special TX descriptor count") 1222 1223 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1224 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1225 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1226 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1227 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1228 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1229 1230 #define CFG_DP_TX_MONITOR_BUF_RING \ 1231 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1232 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1233 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1234 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1235 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1236 1237 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1238 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1239 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1240 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1241 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1242 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1243 1244 #define CFG_DP_TX_MONITOR_DST_RING \ 1245 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1246 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1247 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1248 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1249 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1250 1251 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1252 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1253 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1254 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1255 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1256 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1257 1258 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1259 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1260 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1261 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1262 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1263 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1264 1265 #define CFG_DP_RXDMA_ERR_DST_RING \ 1266 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1267 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1268 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1269 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1270 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1271 1272 #define CFG_DP_PER_PKT_LOGGING \ 1273 CFG_INI_UINT("enable_verbose_debug", \ 1274 0, 0xffff, 0, \ 1275 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 1276 1277 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 1278 CFG_INI_UINT("TxFlowStartQueueOffset", \ 1279 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 1280 CFG_VALUE_OR_DEFAULT, "Start queue offset") 1281 1282 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 1283 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 1284 0, 50, 15, \ 1285 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 1286 1287 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 1288 CFG_INI_UINT("IpaUcTxBufSize", \ 1289 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 1290 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 1291 1292 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 1293 CFG_INI_UINT("IpaUcTxPartitionBase", \ 1294 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1295 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1296 1297 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1298 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1299 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1300 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1301 1302 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1303 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1304 false, "Disable intrs BSS Rx packets") 1305 1306 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1307 CFG_INI_UINT("gEnableDataStallDetection", \ 1308 0, 0xFFFFFFFF, 0x1, \ 1309 CFG_VALUE_OR_DEFAULT, "Enable/Disable Data stall detection") 1310 1311 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1312 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1313 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1314 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1315 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1316 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1317 1318 #define CFG_DP_RX_SW_DESC_NUM \ 1319 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1320 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1321 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1322 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1323 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1324 1325 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1326 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1327 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1328 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1329 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1330 CFG_VALUE_OR_DEFAULT, \ 1331 "DP Rx Flow Search Table Size in number of entries") 1332 1333 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1334 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1335 "Enable/Disable DP Rx Flow Tag") 1336 1337 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1338 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1339 "DP Rx Flow Search Table Is Per PDev") 1340 1341 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1342 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1343 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1344 1345 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1346 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1347 "Enable/Disable tx Per Pkt vdev id check") 1348 1349 #define CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE \ 1350 CFG_INI_BOOL("dp_handle_invalid_decap_type_disable", false, \ 1351 "Enable/Disable DP TLV out of order WAR") 1352 1353 #define CFG_DP_TXMON_SW_PEER_FILTERING \ 1354 CFG_INI_BOOL("tx_litemon_sw_peer_filtering", false, \ 1355 "Enable SW based tx monitor peer fitlering") 1356 1357 #define CFG_DP_POINTER_TIMER_THRESHOLD_RX \ 1358 CFG_INI_UINT("dp_rx_ptr_timer_threshold", \ 1359 0, 0xFFFF, 0, \ 1360 CFG_VALUE_OR_DEFAULT, "RX pointer update timer threshold") 1361 1362 #define CFG_DP_POINTER_NUM_THRESHOLD_RX \ 1363 CFG_INI_UINT("dp_rx_ptr_num_threshold", \ 1364 0, 63, 0, \ 1365 CFG_VALUE_OR_DEFAULT, "RX pointer update entries number threshold") 1366 1367 /* 1368 * <ini> 1369 * dp_rx_fisa_enable - Control Rx datapath FISA 1370 * @Min: 0 1371 * @Max: 1 1372 * @Default: 1 1373 * 1374 * This ini is used to enable DP Rx FISA feature 1375 * 1376 * Related: dp_rx_flow_search_table_size 1377 * 1378 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1379 * 1380 * Usage: Internal 1381 * 1382 * </ini> 1383 */ 1384 #define CFG_DP_RX_FISA_ENABLE \ 1385 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1386 "Enable/Disable DP Rx FISA") 1387 1388 /* 1389 * <ini> 1390 * dp_rx_fisa_lru_del_enable - Control Rx datapath FISA 1391 * @Min: 0 1392 * @Max: 1 1393 * @Default: 1 1394 * 1395 * This ini is used to enable DP Rx FISA lru deletion feature 1396 * 1397 * Related: dp_rx_fisa_enable 1398 * 1399 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1400 * 1401 * Usage: Internal 1402 * 1403 * </ini> 1404 */ 1405 #define CFG_DP_RX_FISA_LRU_DEL_ENABLE \ 1406 CFG_INI_BOOL("dp_rx_fisa_lru_del_enable", true, \ 1407 "Enable/Disable DP Rx FISA LRU deletion") 1408 1409 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1410 CFG_INI_UINT("mon_drop_thresh", \ 1411 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1412 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1413 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1414 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop threshold") 1415 1416 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1417 CFG_INI_UINT("PktlogBufSize", \ 1418 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1419 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1420 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1421 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1422 1423 #define CFG_DP_FULL_MON_MODE \ 1424 CFG_INI_BOOL("full_mon_mode", \ 1425 false, "Full Monitor mode support") 1426 1427 #define CFG_DP_REO_RINGS_MAP \ 1428 CFG_INI_UINT("dp_reo_rings_map", \ 1429 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1430 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1431 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1432 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1433 1434 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1435 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1436 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1437 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1438 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1439 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1440 1441 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1442 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1443 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1444 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1445 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1446 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1447 1448 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1449 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1450 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1451 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1452 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1453 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1454 1455 #define CFG_DP_PEER_EXT_STATS \ 1456 CFG_INI_BOOL("peer_ext_stats", \ 1457 false, "Peer extended stats") 1458 1459 #if defined QCA_ENHANCED_STATS_SUPPORT || defined DP_MLO_LINK_STATS_SUPPORT 1460 #define DEFAULT_PEER_LINK_STATS_VALUE true 1461 #else 1462 #define DEFAULT_PEER_LINK_STATS_VALUE false 1463 #endif /* QCA_ENHANCED_STATS_SUPPORT */ 1464 1465 #define CFG_DP_PEER_LINK_STATS \ 1466 CFG_INI_BOOL("peer_link_stats", \ 1467 DEFAULT_PEER_LINK_STATS_VALUE, "Peer Link stats") 1468 1469 #define CFG_DP_PEER_JITTER_STATS \ 1470 CFG_INI_BOOL("peer_jitter_stats", \ 1471 false, "Peer Jitter stats") 1472 1473 #define CFG_DP_NAPI_SCALE_FACTOR \ 1474 CFG_INI_UINT("dp_napi_scale_factor", \ 1475 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN, \ 1476 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX, \ 1477 WLAN_CFG_DP_NAPI_SCALE_FACTOR, \ 1478 CFG_VALUE_OR_DEFAULT, "NAPI scale factor for DP") 1479 1480 /* 1481 * <ini> 1482 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1483 * @Min: 0 1484 * @Max: 1 1485 * @Default: Default value indicating if checksum should be disabled for 1486 * legacy WLAN modes 1487 * 1488 * This ini is used to disable HW checksum offload capability for legacy 1489 * connections 1490 * 1491 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1492 * 1493 * Usage: Internal 1494 * 1495 * </ini> 1496 */ 1497 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1498 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1499 #endif 1500 1501 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1502 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1503 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1504 "Enable/Disable legacy mode checksum") 1505 1506 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1507 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1508 "Enable/Disable DP RX emergency buffer pool support") 1509 1510 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1511 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1512 "Enable/Disable DP RX refill buffer pool support") 1513 1514 #define CFG_DP_POLL_MODE_ENABLE \ 1515 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1516 "Enable/Disable Polling mode for data path") 1517 1518 #define CFG_DP_RX_FST_IN_CMEM \ 1519 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1520 "Enable/Disable flow search table in CMEM") 1521 /* 1522 * <ini> 1523 * gEnableSWLM - Control DP Software latency manager 1524 * @Min: 0 1525 * @Max: 1 1526 * @Default: 0 1527 * 1528 * This ini is used to enable DP Software latency Manager 1529 * 1530 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1531 * 1532 * Usage: Internal 1533 * 1534 * </ini> 1535 */ 1536 #define CFG_DP_SWLM_ENABLE \ 1537 CFG_INI_BOOL("gEnableSWLM", false, \ 1538 "Enable/Disable DP SWLM") 1539 /* 1540 * <ini> 1541 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1542 * @Min: 0 1543 * @Max: 1 1544 * @Default: 0 1545 * 1546 * This ini is used to control DP Software to perform RX pending check 1547 * before entering WoW mode 1548 * 1549 * Usage: Internal 1550 * 1551 * </ini> 1552 */ 1553 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1554 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1555 false, \ 1556 "enable rx frame pending check in WoW mode") 1557 #define CFG_DP_DELAY_MON_REPLENISH \ 1558 CFG_INI_BOOL("delay_mon_replenish", \ 1559 true, "Delay Monitor Replenish") 1560 1561 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1562 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1563 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1564 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1565 1566 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1567 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1568 false, "Offload vdev stats to HW") 1569 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1570 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1571 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1572 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1573 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1574 CFG_VALUE_OR_DEFAULT, \ 1575 "vdev stats hw offload timer duration") 1576 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1577 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1578 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1579 #else 1580 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1581 #endif 1582 1583 /* 1584 * <ini> 1585 * ghw_cc_enable - enable HW cookie conversion by register 1586 * @Min: 0 1587 * @Max: 1 1588 * @Default: 1 1589 * 1590 * This ini is used to control HW based 20 bits cookie to 64 bits 1591 * Desc virtual address conversion 1592 * 1593 * Usage: Internal 1594 * 1595 * </ini> 1596 */ 1597 #define CFG_DP_HW_CC_ENABLE \ 1598 CFG_INI_BOOL("ghw_cc_enable", \ 1599 true, "Enable/Disable HW cookie conversion") 1600 1601 #ifdef IPA_OFFLOAD 1602 /* 1603 * <ini> 1604 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1605 * @Min: 1024 1606 * @Max: 8096 1607 * @Default: 1024 1608 * 1609 * This ini sets the tcl ring size for IPA 1610 * 1611 * Related: N/A 1612 * 1613 * Supported Feature: IPA 1614 * 1615 * Usage: Internal 1616 * 1617 * </ini> 1618 */ 1619 #define CFG_DP_IPA_TX_RING_SIZE \ 1620 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1621 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1622 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1623 WLAN_CFG_IPA_TX_RING_SIZE, \ 1624 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1625 1626 /* 1627 * <ini> 1628 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1629 * @Min: 1024 1630 * @Max: 8096 1631 * @Default: 1024 1632 * 1633 * This ini sets the tx comp ring size for IPA 1634 * 1635 * Related: N/A 1636 * 1637 * Supported Feature: IPA 1638 * 1639 * Usage: Internal 1640 * 1641 * </ini> 1642 */ 1643 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1644 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1645 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1646 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1647 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1648 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1649 1650 #ifdef IPA_WDI3_TX_TWO_PIPES 1651 /* 1652 * <ini> 1653 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1654 * @Min: 1024 1655 * @Max: 8096 1656 * @Default: 1024 1657 * 1658 * This ini sets the alt tcl ring size for IPA 1659 * 1660 * Related: N/A 1661 * 1662 * Supported Feature: IPA 1663 * 1664 * Usage: Internal 1665 * 1666 * </ini> 1667 */ 1668 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1669 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1670 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1671 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1672 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1673 CFG_VALUE_OR_DEFAULT, \ 1674 "DP IPA TX Alternative Ring Size") 1675 1676 /* 1677 * <ini> 1678 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1679 * @Min: 1024 1680 * @Max: 8096 1681 * @Default: 1024 1682 * 1683 * This ini sets the tx alt comp ring size for IPA 1684 * 1685 * Related: N/A 1686 * 1687 * Supported Feature: IPA 1688 * 1689 * Usage: Internal 1690 * 1691 * </ini> 1692 */ 1693 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1694 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1695 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1696 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1697 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1698 CFG_VALUE_OR_DEFAULT, \ 1699 "DP IPA TX Alternative Completion Ring Size") 1700 1701 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1702 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1703 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1704 1705 #else 1706 #define CFG_DP_IPA_TX_ALT_RING_CFG 1707 #endif 1708 1709 #define CFG_DP_IPA_TX_RING_CFG \ 1710 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1711 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1712 #else 1713 #define CFG_DP_IPA_TX_RING_CFG 1714 #define CFG_DP_IPA_TX_ALT_RING_CFG 1715 #endif 1716 1717 #ifdef WLAN_SUPPORT_PPEDS 1718 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MIN 16 1719 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0x8000 1720 #define WLAN_CFG_NUM_PPEDS_TX_DESC 0x8000 1721 1722 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN 8 1723 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX 256 1724 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI 64 1725 1726 #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MIN 0 1727 #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MAX 0x2000 1728 #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN 0x400 1729 1730 #define CFG_DP_PPEDS_TX_DESC \ 1731 CFG_INI_UINT("dp_ppeds_tx_desc", \ 1732 WLAN_CFG_NUM_PPEDS_TX_DESC_MIN, \ 1733 WLAN_CFG_NUM_PPEDS_TX_DESC_MAX, \ 1734 WLAN_CFG_NUM_PPEDS_TX_DESC, \ 1735 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Descriptors") 1736 1737 #define CFG_DP_PPEDS_TX_DESC_HOTLIST_LEN \ 1738 CFG_INI_UINT("dp_ppeds_tx_desc_hotlist_len", \ 1739 WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MIN, \ 1740 WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MAX, \ 1741 WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN, \ 1742 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Desc hotlist length") 1743 1744 #define CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET \ 1745 CFG_INI_UINT("dp_ppeds_tx_cmp_napi_budget", \ 1746 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN, \ 1747 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX, \ 1748 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI, \ 1749 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Comp handler napi budget") 1750 1751 #define CFG_DP_PPEDS_ENABLE \ 1752 CFG_INI_BOOL("ppe_ds_enable", true, \ 1753 "DP ppe enable flag") 1754 1755 #define CFG_DP_REO2PPE_RING \ 1756 CFG_INI_UINT("dp_reo2ppe_ring", \ 1757 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1758 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1759 WLAN_CFG_REO2PPE_RING_SIZE, \ 1760 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1761 1762 #define CFG_DP_PPE2TCL_RING \ 1763 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1764 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1765 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1766 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1767 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1768 1769 #define CFG_DP_PPEDS_WIFI_SOC_CFG \ 1770 CFG_INI_UINT("ppeds_wifi_soc_cfg", \ 1771 CFG_DP_PPEDS_WIFI_SOC_CFG_NONE, \ 1772 CFG_DP_PPEDS_WIFI_SOC_CFG_ALL, \ 1773 CFG_DP_PPEDS_WIFI_SOC_CFG_DEFAULT, \ 1774 CFG_VALUE_OR_DEFAULT, "PPEDS enable per WiFi SoC") 1775 1776 #define CFG_DP_PPEDS_CONFIG \ 1777 CFG(CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET) \ 1778 CFG(CFG_DP_PPEDS_TX_DESC_HOTLIST_LEN) \ 1779 CFG(CFG_DP_PPEDS_TX_DESC) \ 1780 CFG(CFG_DP_PPEDS_ENABLE) \ 1781 CFG(CFG_DP_REO2PPE_RING) \ 1782 CFG(CFG_DP_PPE2TCL_RING) \ 1783 CFG(CFG_DP_PPEDS_WIFI_SOC_CFG) 1784 #else 1785 #define CFG_DP_PPEDS_CONFIG 1786 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0 1787 #endif 1788 1789 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1790 /* 1791 * <ini> 1792 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1793 * @Min: 0x0 1794 * @Max: 0xFF 1795 * @Default: 0xF 1796 * 1797 * This ini sets Rx ring map for CHIP 0 1798 * 1799 * Usage: Internal 1800 * 1801 * </ini> 1802 */ 1803 #define CFG_DP_MLO_RX_RING_MAP \ 1804 CFG_INI_UINT("dp_mlo_reo_rings_map", \ 1805 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1806 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1807 WLAN_CFG_MLO_RX_RING_MAP, \ 1808 CFG_VALUE_OR_DEFAULT, "DP MLO Rx ring map") 1809 1810 1811 #define CFG_DP_MLO_CONFIG \ 1812 CFG(CFG_DP_MLO_RX_RING_MAP) 1813 #else 1814 #define CFG_DP_MLO_CONFIG 1815 #endif 1816 1817 /* 1818 * <ini> 1819 * dp_mpdu_retry_threshold_1 - threshold to increment mpdu success with retries 1820 * @Min: 0 1821 * @Max: 255 1822 * @Default: 0 1823 * 1824 * This ini entry is used to set first threshold to increment the value of 1825 * mpdu_success_with_retries 1826 * 1827 * Usage: Internal 1828 * 1829 * </ini> 1830 */ 1831 #define CFG_DP_MPDU_RETRY_THRESHOLD_1 \ 1832 CFG_INI_UINT("dp_mpdu_retry_threshold_1", \ 1833 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1834 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1835 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1836 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 1") 1837 1838 /* 1839 * <ini> 1840 * dp_mpdu_retry_threshold_2 - threshold to increment mpdu success with retries 1841 * @Min: 0 1842 * @Max: 255 1843 * @Default: 0 1844 * 1845 * This ini entry is used to set second threshold to increment the value of 1846 * mpdu_success_with_retries 1847 * 1848 * Usage: Internal 1849 * 1850 * </ini> 1851 */ 1852 #define CFG_DP_MPDU_RETRY_THRESHOLD_2 \ 1853 CFG_INI_UINT("dp_mpdu_retry_threshold_2", \ 1854 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1855 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1856 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1857 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 2") 1858 1859 #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES 1860 /* Macro enabling support marking of notify frames by host */ 1861 #define DP_MARK_NOTIFY_FRAME_SUPPORT 1 1862 #else 1863 #define DP_MARK_NOTIFY_FRAME_SUPPORT 0 1864 #endif /* QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES */ 1865 1866 /* 1867 * <ini> 1868 * Host DP AST entries database - Enable/Disable 1869 * 1870 * @Default: 0 1871 * 1872 * This ini enables/disables AST entries database on host 1873 * 1874 * Usage: Internal 1875 * 1876 * </ini> 1877 */ 1878 #define CFG_DP_HOST_AST_DB_ENABLE \ 1879 CFG_INI_BOOL("host_ast_db_enable", false, \ 1880 "Host AST entries database Enable/Disable") 1881 1882 #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 1883 /* 1884 * <ini> 1885 * TX packet inspect for ILP - Enable/Disable 1886 * 1887 * @Default: true 1888 * 1889 * This ini enable/disables TX packet inspection for ILP feature 1890 * 1891 * Usage: Internal 1892 * 1893 * </ini> 1894 */ 1895 #define CFG_TX_PKT_INSPECT_FOR_ILP \ 1896 CFG_INI_BOOL("tx_pkt_inspect_for_ilp", true, \ 1897 "TX packet inspect for ILP") 1898 #define CFG_TX_PKT_INSPECT_FOR_ILP_CFG CFG(CFG_TX_PKT_INSPECT_FOR_ILP) 1899 #else 1900 #define CFG_TX_PKT_INSPECT_FOR_ILP_CFG 1901 #endif 1902 1903 #define CFG_DP \ 1904 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1905 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1906 CFG(CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL) \ 1907 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1908 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1909 CFG(CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL) \ 1910 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1911 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1912 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1913 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1914 CFG(CFG_DP_MAX_CLIENTS) \ 1915 CFG(CFG_DP_MAX_PEER_ID) \ 1916 CFG(CFG_DP_REO_DEST_RINGS) \ 1917 CFG(CFG_DP_TX_COMP_RINGS) \ 1918 CFG(CFG_DP_TCL_DATA_RINGS) \ 1919 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1920 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1921 CFG(CFG_DP_TX_DESC) \ 1922 CFG(CFG_DP_TX_SPL_DESC) \ 1923 CFG(CFG_DP_TX_EXT_DESC) \ 1924 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1925 CFG(CFG_DP_PDEV_RX_RING) \ 1926 CFG(CFG_DP_PDEV_TX_RING) \ 1927 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1928 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1929 CFG(CFG_DP_TX_RING_SIZE) \ 1930 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1931 CFG(CFG_DP_PDEV_LMAC_RING) \ 1932 CFG(CFG_DP_TIME_CONTROL_BP) \ 1933 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1934 CFG(CFG_DP_RX_HASH) \ 1935 CFG(CFG_DP_TSO) \ 1936 CFG(CFG_DP_LRO) \ 1937 CFG(CFG_DP_SG) \ 1938 CFG(CFG_DP_GRO) \ 1939 CFG(CFG_DP_TC_INGRESS_PRIO) \ 1940 CFG(CFG_DP_OL_TX_CSUM) \ 1941 CFG(CFG_DP_OL_RX_CSUM) \ 1942 CFG(CFG_DP_RAWMODE) \ 1943 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1944 CFG(CFG_DP_NAPI) \ 1945 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1946 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1947 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1948 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1949 CFG(CFG_DP_WBM_RELEASE_RING) \ 1950 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1951 CFG(CFG_DP_TCL_STATUS_RING) \ 1952 CFG(CFG_DP_REO_REINJECT_RING) \ 1953 CFG(CFG_DP_RX_RELEASE_RING) \ 1954 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1955 CFG(CFG_DP_RX_DESTINATION_RING) \ 1956 CFG(CFG_DP_REO_CMD_RING) \ 1957 CFG(CFG_DP_REO_STATUS_RING) \ 1958 CFG(CFG_DP_RXDMA_BUF_RING) \ 1959 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1960 CFG(CFG_DP_RXDMA_REFILL_LT_DISABLE) \ 1961 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1962 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1963 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1964 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1965 CFG(CFG_DP_TX_SPL_DEVICE_LIMIT) \ 1966 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1967 CFG(CFG_DP_TX_DESC_GLOBAL_COUNT) \ 1968 CFG(CFG_DP_SPCL_TX_DESC_GLOBAL_COUNT) \ 1969 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1970 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1971 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1972 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1973 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1974 CFG(CFG_DP_PER_PKT_LOGGING) \ 1975 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1976 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1977 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1978 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1979 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1980 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1981 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1982 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1983 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1984 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1985 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1986 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1987 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1988 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1989 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1990 CFG(CFG_DP_RX_FISA_ENABLE) \ 1991 CFG(CFG_DP_RX_FISA_LRU_DEL_ENABLE) \ 1992 CFG(CFG_DP_FULL_MON_MODE) \ 1993 CFG(CFG_DP_REO_RINGS_MAP) \ 1994 CFG(CFG_DP_PEER_EXT_STATS) \ 1995 CFG(CFG_DP_PEER_JITTER_STATS) \ 1996 CFG(CFG_DP_PEER_LINK_STATS) \ 1997 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1998 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1999 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 2000 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 2001 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 2002 CFG(CFG_DP_POLL_MODE_ENABLE) \ 2003 CFG(CFG_DP_SWLM_ENABLE) \ 2004 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 2005 CFG(CFG_DP_RX_FST_IN_CMEM) \ 2006 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 2007 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 2008 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 2009 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 2010 CFG(CFG_DP_HW_CC_ENABLE) \ 2011 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 2012 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 2013 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 2014 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_1) \ 2015 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_2) \ 2016 CFG_DP_IPA_TX_RING_CFG \ 2017 CFG_DP_PPEDS_CONFIG \ 2018 CFG_DP_IPA_TX_ALT_RING_CFG \ 2019 CFG_DP_MLO_CONFIG \ 2020 CFG_DP_INI_SECTION_PARAMS \ 2021 CFG_DP_VDEV_STATS_HW_OFFLOAD \ 2022 CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) \ 2023 CFG(CFG_DP_NAPI_SCALE_FACTOR) \ 2024 CFG(CFG_DP_HOST_AST_DB_ENABLE) \ 2025 CFG_DP_SAWF_STATS_CONFIG \ 2026 CFG(CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE) \ 2027 CFG(CFG_DP_TXMON_SW_PEER_FILTERING) \ 2028 CFG_TX_PKT_INSPECT_FOR_ILP_CFG \ 2029 CFG(CFG_DP_POINTER_TIMER_THRESHOLD_RX) \ 2030 CFG(CFG_DP_POINTER_NUM_THRESHOLD_RX) 2031 #endif /* _CFG_DP_H_ */ 2032