1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #ifdef IPA_OFFLOAD 52 /* Size of TCL TX Ring */ 53 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 54 #define WLAN_CFG_TX_RING_SIZE 2048 55 #else 56 #define WLAN_CFG_TX_RING_SIZE 1024 57 #endif 58 59 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 1024 60 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 61 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 8096 62 63 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 1024 64 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 65 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 8096 66 67 #ifdef IPA_WDI3_TX_TWO_PIPES 68 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 1024 69 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 70 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 8096 71 72 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 1024 73 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 8096 75 #endif 76 77 #define WLAN_CFG_PER_PDEV_TX_RING 0 78 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 79 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 80 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 81 #else 82 #define WLAN_CFG_TX_RING_SIZE 512 83 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 84 #define WLAN_CFG_PER_PDEV_TX_RING 1 85 #else 86 #define WLAN_CFG_PER_PDEV_TX_RING 0 87 #endif 88 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 89 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 90 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 91 #endif /* IPA_OFFLOAD */ 92 93 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 94 #define WLAN_CFG_PER_PDEV_RX_RING 0 95 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 96 #define WLAN_LRO_ENABLE 0 97 #ifdef QCA_WIFI_QCA6750 98 #define WLAN_CFG_MAC_PER_TARGET 1 99 #else 100 #define WLAN_CFG_MAC_PER_TARGET 2 101 #endif 102 103 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 104 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 105 106 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 107 #define WLAN_CFG_NUM_TX_DESC 4096 108 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 109 #else 110 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 111 112 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 113 #define WLAN_CFG_NUM_TX_DESC 1024 114 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 115 #endif 116 117 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 118 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 119 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 120 121 /* Interrupt Mitigation - Timer threshold in us */ 122 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 123 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 124 125 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 126 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 127 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 128 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 129 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 130 #else 131 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 132 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 133 #endif 134 #endif /* WLAN_MAX_PDEVS */ 135 136 #ifdef NBUF_MEMORY_DEBUG 137 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 138 #else 139 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 140 #endif 141 142 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 143 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 144 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 145 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 146 147 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 148 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 149 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 150 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 151 152 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 153 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 154 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 155 156 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 157 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 158 159 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 160 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 161 162 #define WLAN_CFG_TX_RING_SIZE_MIN 512 163 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 164 165 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 166 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 167 168 #define WLAN_CFG_NUM_TX_DESC_MIN 16 169 #define WLAN_CFG_NUM_TX_DESC_MAX 0x10000 170 171 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 172 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 173 174 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 175 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 176 177 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 178 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 179 180 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 181 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 182 183 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 184 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 185 186 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 187 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 188 189 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 190 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 191 192 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 193 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 194 195 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 196 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 197 198 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 199 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 200 201 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 202 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 203 204 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 205 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 206 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 207 208 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 209 210 /* Per vdev pools */ 211 #define WLAN_CFG_NUM_TX_DESC_POOL 3 212 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 213 214 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 215 216 #ifdef TX_PER_PDEV_DESC_POOL 217 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 218 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 219 220 #else /* TX_PER_PDEV_DESC_POOL */ 221 222 #define WLAN_CFG_NUM_TX_DESC_POOL 3 223 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 224 225 #endif /* TX_PER_PDEV_DESC_POOL */ 226 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 227 228 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 229 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 230 231 #define WLAN_CFG_HTT_PKT_TYPE 2 232 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 233 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 234 235 #define WLAN_CFG_MAX_PEER_ID 64 236 #define WLAN_CFG_MAX_PEER_ID_MIN 64 237 #define WLAN_CFG_MAX_PEER_ID_MAX 64 238 239 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 240 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 241 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 242 243 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 244 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 245 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 246 247 #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 248 #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 249 #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 250 251 #if defined(CONFIG_BERYLLIUM) 252 #define WLAN_CFG_NUM_REO_DEST_RING 8 253 #else 254 #define WLAN_CFG_NUM_REO_DEST_RING 4 255 #endif 256 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 257 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 258 259 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 260 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 261 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 262 263 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 264 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 265 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 266 267 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 268 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 269 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 270 271 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 272 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 273 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 274 275 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 276 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 277 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 278 279 #if defined(QCA_WIFI_QCA6290) 280 #define WLAN_CFG_REO_DST_RING_SIZE 1024 281 #else 282 #define WLAN_CFG_REO_DST_RING_SIZE 2048 283 #endif 284 285 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 286 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 287 288 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 289 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 290 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 291 292 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 293 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 294 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 295 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 296 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 297 #else 298 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192 299 #endif 300 301 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 302 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 303 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 304 305 #define WLAN_CFG_REO_CMD_RING_SIZE 128 306 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 307 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 308 309 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 310 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 311 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 312 313 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 314 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 315 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 4096 316 317 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 318 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 319 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 16384 320 321 #define WLAN_CFG_TX_DESC_LIMIT_0 0 322 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 323 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 324 325 #define WLAN_CFG_TX_DESC_LIMIT_1 0 326 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 327 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 328 329 #define WLAN_CFG_TX_DESC_LIMIT_2 0 330 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 331 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 332 333 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 334 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 335 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 336 337 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 338 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 339 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 340 341 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 342 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 343 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 344 345 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 346 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 347 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 348 349 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 350 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 351 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 352 353 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 354 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 355 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 8192 356 357 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 358 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 359 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 360 361 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 362 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 363 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 364 365 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 366 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 367 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 368 369 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 370 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 371 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 372 373 /** 374 * Allocate as many RX descriptors as buffers in the SW2RXDMA 375 * ring. This value may need to be tuned later. 376 */ 377 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 378 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 379 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 380 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 381 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 382 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 383 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 384 385 /** 386 * For low memory AP cases using 1 will reduce the rx descriptors memory req 387 */ 388 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 389 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 390 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 391 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 392 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 393 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 394 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 395 396 /** 397 * AP use cases need to allocate more RX Descriptors than the number of 398 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account 399 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 400 * multiplication factor of 3, to allocate three times as many RX descriptors 401 * as RX buffers. 402 */ 403 #else 404 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 405 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 406 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 407 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 408 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 409 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 12288 410 #endif 411 412 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 413 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 414 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 415 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 416 417 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 418 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 419 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 420 421 #ifdef IPA_OFFLOAD 422 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 423 #else 424 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 425 #endif 426 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 427 #if defined(CONFIG_BERYLLIUM) 428 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xFF 429 #else 430 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 431 #endif 432 433 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 434 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 435 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 436 437 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 438 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 439 440 #define WLAN_CFG_REO2PPE_RING_SIZE 1024 441 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 442 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 1024 443 444 #define WLAN_CFG_PPE2TCL_RING_SIZE 1024 445 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 446 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 1024 447 448 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 449 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 450 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 451 452 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 453 #define WLAN_CFG_MLO_RX_RING_MAP 0xF 454 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 455 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 456 #endif 457 458 #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 459 #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 460 #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 461 462 #define CFG_DP_MPDU_RETRY_THRESHOLD_MIN 0 463 #define CFG_DP_MPDU_RETRY_THRESHOLD_MAX 255 464 #define CFG_DP_MPDU_RETRY_THRESHOLD 0 465 466 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR 0 467 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN 0 468 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX 4 469 470 /* 471 * <ini> 472 * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 473 * @Min: 0 474 * @Max: 512 MB 475 * @Default: 0 (disabled) 476 * 477 * This ini entry is used to set a max limit beyond which frames 478 * are dropped by Tx capture. User needs to set a non-zero value 479 * to enable it. 480 * 481 * Usage: External 482 * 483 * </ini> 484 */ 485 #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 486 CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 487 WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 488 WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 489 WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 490 CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 491 492 /* DP INI Declarations */ 493 #define CFG_DP_HTT_PACKET_TYPE \ 494 CFG_INI_UINT("dp_htt_packet_type", \ 495 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 496 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 497 WLAN_CFG_HTT_PKT_TYPE, \ 498 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 499 500 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 501 CFG_INI_UINT("dp_int_batch_threshold_other", \ 502 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 503 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 504 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 505 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 506 507 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 508 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 509 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 510 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 511 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 512 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 513 514 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 515 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 516 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 517 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 518 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 519 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 520 521 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 522 CFG_INI_UINT("dp_int_timer_threshold_other", \ 523 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 524 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 525 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 526 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 527 528 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 529 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 530 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 531 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 532 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 533 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 534 535 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 536 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 537 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 538 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 539 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 540 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 541 542 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 543 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 544 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 545 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 546 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 547 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 548 549 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 550 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 551 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 552 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 553 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 554 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 555 556 #define CFG_DP_MAX_ALLOC_SIZE \ 557 CFG_INI_UINT("dp_max_alloc_size", \ 558 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 559 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 560 WLAN_CFG_MAX_ALLOC_SIZE, \ 561 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 562 563 #define CFG_DP_MAX_CLIENTS \ 564 CFG_INI_UINT("dp_max_clients", \ 565 WLAN_CFG_MAX_CLIENTS_MIN, \ 566 WLAN_CFG_MAX_CLIENTS_MAX, \ 567 WLAN_CFG_MAX_CLIENTS, \ 568 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 569 570 #define CFG_DP_MAX_PEER_ID \ 571 CFG_INI_UINT("dp_max_peer_id", \ 572 WLAN_CFG_MAX_PEER_ID_MIN, \ 573 WLAN_CFG_MAX_PEER_ID_MAX, \ 574 WLAN_CFG_MAX_PEER_ID, \ 575 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 576 577 #define CFG_DP_REO_DEST_RINGS \ 578 CFG_INI_UINT("dp_reo_dest_rings", \ 579 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 580 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 581 WLAN_CFG_NUM_REO_DEST_RING, \ 582 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 583 584 #define CFG_DP_TX_COMP_RINGS \ 585 CFG_INI_UINT("dp_tx_comp_rings", \ 586 WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 587 WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 588 WLAN_CFG_NUM_TX_COMP_RINGS, \ 589 CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 590 591 #define CFG_DP_TCL_DATA_RINGS \ 592 CFG_INI_UINT("dp_tcl_data_rings", \ 593 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 594 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 595 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 596 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 597 598 #define CFG_DP_NSS_REO_DEST_RINGS \ 599 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 600 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 601 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 602 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 603 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 604 605 #define CFG_DP_NSS_TCL_DATA_RINGS \ 606 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 607 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 608 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 609 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 610 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 611 612 #define CFG_DP_TX_DESC \ 613 CFG_INI_UINT("dp_tx_desc", \ 614 WLAN_CFG_NUM_TX_DESC_MIN, \ 615 WLAN_CFG_NUM_TX_DESC_MAX, \ 616 WLAN_CFG_NUM_TX_DESC, \ 617 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 618 619 #define CFG_DP_TX_EXT_DESC \ 620 CFG_INI_UINT("dp_tx_ext_desc", \ 621 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 622 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 623 WLAN_CFG_NUM_TX_EXT_DESC, \ 624 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 625 626 #define CFG_DP_TX_EXT_DESC_POOLS \ 627 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 628 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 629 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 630 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 631 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 632 633 #define CFG_DP_PDEV_RX_RING \ 634 CFG_INI_UINT("dp_pdev_rx_ring", \ 635 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 636 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 637 WLAN_CFG_PER_PDEV_RX_RING, \ 638 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 639 640 #define CFG_DP_PDEV_TX_RING \ 641 CFG_INI_UINT("dp_pdev_tx_ring", \ 642 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 643 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 644 WLAN_CFG_PER_PDEV_TX_RING, \ 645 CFG_VALUE_OR_DEFAULT, \ 646 "DP PDEV Tx Ring") 647 648 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 649 CFG_INI_UINT("dp_rx_defrag_timeout", \ 650 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 651 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 652 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 653 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 654 655 #define CFG_DP_TX_COMPL_RING_SIZE \ 656 CFG_INI_UINT("dp_tx_compl_ring_size", \ 657 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 658 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 659 WLAN_CFG_TX_COMP_RING_SIZE, \ 660 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 661 662 #define CFG_DP_TX_RING_SIZE \ 663 CFG_INI_UINT("dp_tx_ring_size", \ 664 WLAN_CFG_TX_RING_SIZE_MIN,\ 665 WLAN_CFG_TX_RING_SIZE_MAX,\ 666 WLAN_CFG_TX_RING_SIZE,\ 667 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 668 669 #define CFG_DP_NSS_COMP_RING_SIZE \ 670 CFG_INI_UINT("dp_nss_comp_ring_size", \ 671 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 672 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 673 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 674 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 675 676 #define CFG_DP_PDEV_LMAC_RING \ 677 CFG_INI_UINT("dp_pdev_lmac_ring", \ 678 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 679 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 680 WLAN_CFG_PER_PDEV_LMAC_RING, \ 681 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 682 /* 683 * <ini> 684 * dp_rx_pending_hl_threshold - High threshold of frame number to start 685 * frame dropping scheme 686 * @Min: 0 687 * @Max: 524288 688 * @Default: 393216 689 * 690 * This ini entry is used to set a high limit threshold to start frame 691 * dropping scheme 692 * 693 * Usage: External 694 * 695 * </ini> 696 */ 697 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 698 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 699 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 700 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 701 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 702 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 703 704 /* 705 * <ini> 706 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 707 * frame dropping scheme 708 * @Min: 100 709 * @Max: 524288 710 * @Default: 393216 711 * 712 * This ini entry is used to set a low limit threshold to stop frame 713 * dropping scheme 714 * 715 * Usage: External 716 * 717 * </ini> 718 */ 719 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 720 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 721 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 722 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 723 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 724 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 725 726 #define CFG_DP_BASE_HW_MAC_ID \ 727 CFG_INI_UINT("dp_base_hw_macid", \ 728 0, 1, 1, \ 729 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 730 731 #define CFG_DP_RX_HASH \ 732 CFG_INI_BOOL("dp_rx_hash", true, \ 733 "DP Rx Hash") 734 735 #define CFG_DP_TSO \ 736 CFG_INI_BOOL("TSOEnable", false, \ 737 "DP TSO Enabled") 738 739 #define CFG_DP_LRO \ 740 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 741 "DP LRO Enable") 742 743 #ifdef WLAN_USE_CONFIG_PARAMS 744 /* 745 * <ini> 746 * dp_tx_desc_use_512p - Use 512M tx descriptor size 747 * @Min: 0 748 * @Max: 1 749 * @Default: 0 750 * 751 * This ini entry is used as flag to use 512M tx descriptor size or not 752 * 753 * Usage: Internal 754 * 755 * </ini> 756 */ 757 #define CFG_DP_TX_DESC_512P \ 758 CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 759 "DP TX DESC PINE SPECIFIC") 760 761 /* 762 * <ini> 763 * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 764 * @Min: 0 765 * @Max: 1 766 * @Default: 0 767 * 768 * This ini entry is used as flag to use 3 Radio NSS com ring size or not 769 * 770 * Usage: Internal 771 * 772 * </ini> 773 */ 774 #define CFG_DP_NSS_3RADIO_RING \ 775 CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 776 "DP NSS 3 RADIO RING SIZE") 777 778 /* 779 * <ini> 780 * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 781 * @Min: 0 782 * @Max: 1 783 * @Default: 0 784 * 785 * This ini entry is used as flag to update monitor status ring as 512M profile 786 * 787 * Usage: Internal 788 * 789 * </ini> 790 */ 791 #define CFG_DP_MON_STATUS_512M \ 792 CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 793 "DP MON STATUS RING SIZE PER 512M PROFILE") 794 795 /* 796 * <ini> 797 * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 798 * @Min: 0 799 * @Max: 1 800 * @Default: 0 801 * 802 * This ini entry is used as flag to reduce monitor rings size as those used 803 * in case of 2 Tx/RxChains 804 * 805 * Usage: Internal 806 * 807 * </ini> 808 */ 809 #define CFG_DP_MON_2CHAIN_RING \ 810 CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 811 "DP MON UPDATE RINGS FOR 2CHAIN") 812 813 /* 814 * <ini> 815 * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 816 * @Min: 0 817 * @Max: 1 818 * @Default: 0 819 * 820 * This ini entry is used as flag to reduce monitor rings size as those used 821 * in case of 4 Tx/RxChains 822 * 823 * Usage: Internal 824 * 825 * </ini> 826 */ 827 #define CFG_DP_MON_4CHAIN_RING \ 828 CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 829 "DP MON UPDATE RINGS FOR 4CHAIN") 830 831 /* 832 * <ini> 833 * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 834 * @Min: 0 835 * @Max: 1 836 * @Default: 0 837 * 838 * This ini entry is used as flag to update RDP reo map based on 4 Radio config 839 * 840 * Usage: Internal 841 * 842 * </ini> 843 */ 844 #define CFG_DP_4RADIO_RDP_REO \ 845 CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 846 false, "Update REO destination mapping for 4radio") 847 848 #define CFG_DP_INI_SECTION_PARAMS \ 849 CFG(CFG_DP_NSS_3RADIO_RING) \ 850 CFG(CFG_DP_TX_DESC_512P) \ 851 CFG(CFG_DP_MON_STATUS_512M) \ 852 CFG(CFG_DP_MON_2CHAIN_RING) \ 853 CFG(CFG_DP_MON_4CHAIN_RING) \ 854 CFG(CFG_DP_4RADIO_RDP_REO) 855 #else 856 #define CFG_DP_INI_SECTION_PARAMS 857 #endif 858 859 /* 860 * <ini> 861 * CFG_DP_SG - Enable the SG feature standalonely 862 * @Min: 0 863 * @Max: 1 864 * @Default: 1 865 * 866 * This ini entry is used to enable/disable SG feature standalonely. 867 * Also does Rome support SG on TX, lithium does not. 868 * For example the lithium does not support SG on UDP frames. 869 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 870 * 871 * Usage: External 872 * 873 * </ini> 874 */ 875 #define CFG_DP_SG \ 876 CFG_INI_BOOL("dp_sg_support", false, \ 877 "DP SG Enable") 878 879 #define WLAN_CFG_GRO_ENABLE_MIN 0 880 #define WLAN_CFG_GRO_ENABLE_MAX 3 881 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 882 #define DP_GRO_ENABLE_BIT_SET BIT(0) 883 #define DP_TC_BASED_DYNAMIC_GRO BIT(1) 884 885 /* 886 * <ini> 887 * CFG_DP_GRO - Enable the GRO feature standalonely 888 * @Min: 0 889 * @Max: 3 890 * @Default: 0 891 * 892 * This ini entry is used to enable/disable GRO feature standalonely. 893 * Value 0: Disable GRO feature 894 * Value 1: Enable GRO feature always 895 * Value 3: Enable GRO dynamic feature where TC rule can control GRO 896 * behavior 897 * 898 * Usage: External 899 * 900 * </ini> 901 */ 902 #define CFG_DP_GRO \ 903 CFG_INI_UINT("GROEnable", \ 904 WLAN_CFG_GRO_ENABLE_MIN, \ 905 WLAN_CFG_GRO_ENABLE_MAX, \ 906 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 907 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 908 909 #define WLAN_CFG_TC_INGRESS_PRIO_MIN 0 910 #define WLAN_CFG_TC_INGRESS_PRIO_MAX 0xFFFF 911 #define WLAN_CFG_TC_INGRESS_PRIO_DEFAULT 0 912 913 #define CFG_DP_TC_INGRESS_PRIO \ 914 CFG_INI_UINT("tc_ingress_prio", \ 915 WLAN_CFG_TC_INGRESS_PRIO_MIN, \ 916 WLAN_CFG_TC_INGRESS_PRIO_MAX, \ 917 WLAN_CFG_TC_INGRESS_PRIO_DEFAULT, \ 918 CFG_VALUE_OR_DEFAULT, "DP tc ingress prio") 919 920 #define CFG_DP_OL_TX_CSUM \ 921 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 922 "DP tx csum Enable") 923 924 #define CFG_DP_OL_RX_CSUM \ 925 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 926 "DP rx csum Enable") 927 928 #define CFG_DP_RAWMODE \ 929 CFG_INI_BOOL("dp_rawmode_support", false, \ 930 "DP rawmode Enable") 931 932 #define CFG_DP_PEER_FLOW_CTRL \ 933 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 934 "DP peer flow ctrl Enable") 935 936 #define CFG_DP_NAPI \ 937 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 938 "DP Napi Enabled") 939 /* 940 * <ini> 941 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 942 * @Min: 0 943 * @Max: 1 944 * @Default: 1 945 * 946 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 947 * This includes P2P device mode, P2P client mode and P2P GO mode. 948 * The feature is enabled by default. To disable TX checksum for P2P, add the 949 * following entry in ini file: 950 * gEnableP2pIpTcpUdpChecksumOffload=0 951 * 952 * Usage: External 953 * 954 * </ini> 955 */ 956 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 957 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 958 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 959 960 /* 961 * <ini> 962 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 963 * @Min: 0 964 * @Max: 1 965 * @Default: 1 966 * 967 * Usage: External 968 * 969 * </ini> 970 */ 971 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 972 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 973 "DP TCP UDP Checksum Offload for NAN mode") 974 975 /* 976 * <ini> 977 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 978 * @Min: 0 979 * @Max: 1 980 * @Default: 1 981 * 982 * Usage: External 983 * 984 * </ini> 985 */ 986 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 987 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 988 "DP TCP UDP Checksum Offload") 989 990 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 991 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 992 "DP Defrag Timeout Check") 993 994 #define CFG_DP_WBM_RELEASE_RING \ 995 CFG_INI_UINT("dp_wbm_release_ring", \ 996 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 997 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 998 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 999 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 1000 1001 #define CFG_DP_TCL_CMD_CREDIT_RING \ 1002 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 1003 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 1004 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 1005 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 1006 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 1007 1008 #define CFG_DP_TCL_STATUS_RING \ 1009 CFG_INI_UINT("dp_tcl_status_ring",\ 1010 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 1011 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 1012 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 1013 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 1014 1015 #define CFG_DP_REO_REINJECT_RING \ 1016 CFG_INI_UINT("dp_reo_reinject_ring", \ 1017 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 1018 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 1019 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1020 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1021 1022 #define CFG_DP_RX_RELEASE_RING \ 1023 CFG_INI_UINT("dp_rx_release_ring", \ 1024 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1025 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1026 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1027 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1028 1029 #define CFG_DP_RX_DESTINATION_RING \ 1030 CFG_INI_UINT("dp_reo_dst_ring", \ 1031 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 1032 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 1033 WLAN_CFG_REO_DST_RING_SIZE, \ 1034 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 1035 1036 #define CFG_DP_REO_EXCEPTION_RING \ 1037 CFG_INI_UINT("dp_reo_exception_ring", \ 1038 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1039 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1040 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1041 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1042 1043 #define CFG_DP_REO_CMD_RING \ 1044 CFG_INI_UINT("dp_reo_cmd_ring", \ 1045 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1046 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1047 WLAN_CFG_REO_CMD_RING_SIZE, \ 1048 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1049 1050 #define CFG_DP_REO_STATUS_RING \ 1051 CFG_INI_UINT("dp_reo_status_ring", \ 1052 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1053 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1054 WLAN_CFG_REO_STATUS_RING_SIZE, \ 1055 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1056 1057 #define CFG_DP_RXDMA_BUF_RING \ 1058 CFG_INI_UINT("dp_rxdma_buf_ring", \ 1059 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1060 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1061 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1062 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1063 1064 #define CFG_DP_RXDMA_REFILL_RING \ 1065 CFG_INI_UINT("dp_rxdma_refill_ring", \ 1066 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1067 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1068 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1069 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1070 1071 #define CFG_DP_TX_DESC_LIMIT_0 \ 1072 CFG_INI_UINT("dp_tx_desc_limit_0", \ 1073 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 1074 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 1075 WLAN_CFG_TX_DESC_LIMIT_0, \ 1076 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 1077 1078 #define CFG_DP_TX_DESC_LIMIT_1 \ 1079 CFG_INI_UINT("dp_tx_desc_limit_1", \ 1080 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 1081 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 1082 WLAN_CFG_TX_DESC_LIMIT_1, \ 1083 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 1084 1085 #define CFG_DP_TX_DESC_LIMIT_2 \ 1086 CFG_INI_UINT("dp_tx_desc_limit_2", \ 1087 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 1088 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 1089 WLAN_CFG_TX_DESC_LIMIT_2, \ 1090 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 1091 1092 #define CFG_DP_TX_DEVICE_LIMIT \ 1093 CFG_INI_UINT("dp_tx_device_limit", \ 1094 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1095 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1096 WLAN_CFG_TX_DEVICE_LIMIT, \ 1097 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1098 1099 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1100 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1101 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1102 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1103 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1104 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1105 1106 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1107 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1108 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1109 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1110 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1111 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1112 1113 #define CFG_DP_TX_MONITOR_BUF_RING \ 1114 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1115 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1116 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1117 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1118 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1119 1120 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1121 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1122 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1123 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1124 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1125 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1126 1127 #define CFG_DP_TX_MONITOR_DST_RING \ 1128 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1129 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1130 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1131 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1132 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1133 1134 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1135 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1136 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1137 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1138 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1139 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1140 1141 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1142 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1143 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1144 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1145 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1146 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1147 1148 #define CFG_DP_RXDMA_ERR_DST_RING \ 1149 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1150 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1151 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1152 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1153 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1154 1155 #define CFG_DP_PER_PKT_LOGGING \ 1156 CFG_INI_UINT("enable_verbose_debug", \ 1157 0, 0xffff, 0, \ 1158 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 1159 1160 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 1161 CFG_INI_UINT("TxFlowStartQueueOffset", \ 1162 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 1163 CFG_VALUE_OR_DEFAULT, "Start queue offset") 1164 1165 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 1166 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 1167 0, 50, 15, \ 1168 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 1169 1170 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 1171 CFG_INI_UINT("IpaUcTxBufSize", \ 1172 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 1173 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 1174 1175 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 1176 CFG_INI_UINT("IpaUcTxPartitionBase", \ 1177 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1178 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1179 1180 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1181 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1182 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1183 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1184 1185 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1186 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1187 false, "Disable intrs BSS Rx packets") 1188 1189 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1190 CFG_INI_UINT("gEnableDataStallDetection", \ 1191 0, 0xFFFFFFFF, 0x1, \ 1192 CFG_VALUE_OR_DEFAULT, "Enable/Disable Data stall detection") 1193 1194 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1195 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1196 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1197 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1198 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1199 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1200 1201 #define CFG_DP_RX_SW_DESC_NUM \ 1202 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1203 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1204 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1205 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1206 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1207 1208 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1209 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1210 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1211 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1212 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1213 CFG_VALUE_OR_DEFAULT, \ 1214 "DP Rx Flow Search Table Size in number of entries") 1215 1216 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1217 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1218 "Enable/Disable DP Rx Flow Tag") 1219 1220 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1221 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1222 "DP Rx Flow Search Table Is Per PDev") 1223 1224 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1225 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1226 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1227 1228 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1229 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1230 "Enable/Disable tx Per Pkt vdev id check") 1231 1232 /* 1233 * <ini> 1234 * dp_rx_fisa_enable - Control Rx datapath FISA 1235 * @Min: 0 1236 * @Max: 1 1237 * @Default: 1 1238 * 1239 * This ini is used to enable DP Rx FISA feature 1240 * 1241 * Related: dp_rx_flow_search_table_size 1242 * 1243 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1244 * 1245 * Usage: Internal 1246 * 1247 * </ini> 1248 */ 1249 #define CFG_DP_RX_FISA_ENABLE \ 1250 CFG_INI_BOOL("dp_rx_fisa_enable", true, \ 1251 "Enable/Disable DP Rx FISA") 1252 1253 /* 1254 * <ini> 1255 * dp_rx_fisa_lru_del_enable - Control Rx datapath FISA 1256 * @Min: 0 1257 * @Max: 1 1258 * @Default: 1 1259 * 1260 * This ini is used to enable DP Rx FISA lru deletion feature 1261 * 1262 * Related: dp_rx_fisa_enable 1263 * 1264 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1265 * 1266 * Usage: Internal 1267 * 1268 * </ini> 1269 */ 1270 #define CFG_DP_RX_FISA_LRU_DEL_ENABLE \ 1271 CFG_INI_BOOL("dp_rx_fisa_lru_del_enable", true, \ 1272 "Enable/Disable DP Rx FISA LRU deletion") 1273 1274 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1275 CFG_INI_UINT("mon_drop_thresh", \ 1276 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1277 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1278 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1279 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold") 1280 1281 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1282 CFG_INI_UINT("PktlogBufSize", \ 1283 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1284 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1285 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1286 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1287 1288 #define CFG_DP_FULL_MON_MODE \ 1289 CFG_INI_BOOL("full_mon_mode", \ 1290 false, "Full Monitor mode support") 1291 1292 #define CFG_DP_REO_RINGS_MAP \ 1293 CFG_INI_UINT("dp_reo_rings_map", \ 1294 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1295 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1296 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1297 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1298 1299 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1300 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1301 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1302 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1303 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1304 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1305 1306 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1307 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1308 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1309 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1310 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1311 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1312 1313 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1314 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1315 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1316 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1317 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1318 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1319 1320 #define CFG_DP_PEER_EXT_STATS \ 1321 CFG_INI_BOOL("peer_ext_stats", \ 1322 false, "Peer extended stats") 1323 1324 #define CFG_DP_NAPI_SCALE_FACTOR \ 1325 CFG_INI_UINT("dp_napi_scale_factor", \ 1326 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN, \ 1327 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX, \ 1328 WLAN_CFG_DP_NAPI_SCALE_FACTOR, \ 1329 CFG_VALUE_OR_DEFAULT, "NAPI scale factor for DP") 1330 1331 /* 1332 * <ini> 1333 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1334 * @Min: 0 1335 * @Max: 1 1336 * @Default: Default value indicating if checksum should be disabled for 1337 * legacy WLAN modes 1338 * 1339 * This ini is used to disable HW checksum offload capability for legacy 1340 * connections 1341 * 1342 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1343 * 1344 * Usage: Internal 1345 * 1346 * </ini> 1347 */ 1348 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1349 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1350 #endif 1351 1352 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1353 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1354 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1355 "Enable/Disable legacy mode checksum") 1356 1357 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1358 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1359 "Enable/Disable DP RX emergency buffer pool support") 1360 1361 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1362 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1363 "Enable/Disable DP RX refill buffer pool support") 1364 1365 #define CFG_DP_POLL_MODE_ENABLE \ 1366 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1367 "Enable/Disable Polling mode for data path") 1368 1369 #define CFG_DP_RX_FST_IN_CMEM \ 1370 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1371 "Enable/Disable flow search table in CMEM") 1372 /* 1373 * <ini> 1374 * gEnableSWLM - Control DP Software latency manager 1375 * @Min: 0 1376 * @Max: 1 1377 * @Default: 0 1378 * 1379 * This ini is used to enable DP Software latency Manager 1380 * 1381 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1382 * 1383 * Usage: Internal 1384 * 1385 * </ini> 1386 */ 1387 #define CFG_DP_SWLM_ENABLE \ 1388 CFG_INI_BOOL("gEnableSWLM", false, \ 1389 "Enable/Disable DP SWLM") 1390 /* 1391 * <ini> 1392 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1393 * @Min: 0 1394 * @Max: 1 1395 * @Default: 0 1396 * 1397 * This ini is used to control DP Software to perform RX pending check 1398 * before entering WoW mode 1399 * 1400 * Usage: Internal 1401 * 1402 * </ini> 1403 */ 1404 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1405 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1406 false, \ 1407 "enable rx frame pending check in WoW mode") 1408 #define CFG_DP_DELAY_MON_REPLENISH \ 1409 CFG_INI_BOOL("delay_mon_replenish", \ 1410 true, "Delay Monitor Replenish") 1411 1412 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1413 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1414 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1415 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1416 1417 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1418 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1419 false, "Offload vdev stats to HW") 1420 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1421 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1422 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1423 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1424 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1425 CFG_VALUE_OR_DEFAULT, \ 1426 "vdev stats hw offload timer duration") 1427 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1428 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1429 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1430 #else 1431 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1432 #endif 1433 1434 /* 1435 * <ini> 1436 * ghw_cc_enable - enable HW cookie conversion by register 1437 * @Min: 0 1438 * @Max: 1 1439 * @Default: 1 1440 * 1441 * This ini is used to control HW based 20 bits cookie to 64 bits 1442 * Desc virtual address conversion 1443 * 1444 * Usage: Internal 1445 * 1446 * </ini> 1447 */ 1448 #define CFG_DP_HW_CC_ENABLE \ 1449 CFG_INI_BOOL("ghw_cc_enable", \ 1450 true, "Enable/Disable HW cookie conversion") 1451 1452 #ifdef IPA_OFFLOAD 1453 /* 1454 * <ini> 1455 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1456 * @Min: 1024 1457 * @Max: 8096 1458 * @Default: 1024 1459 * 1460 * This ini sets the tcl ring size for IPA 1461 * 1462 * Related: N/A 1463 * 1464 * Supported Feature: IPA 1465 * 1466 * Usage: Internal 1467 * 1468 * </ini> 1469 */ 1470 #define CFG_DP_IPA_TX_RING_SIZE \ 1471 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1472 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1473 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1474 WLAN_CFG_IPA_TX_RING_SIZE, \ 1475 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1476 1477 /* 1478 * <ini> 1479 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1480 * @Min: 1024 1481 * @Max: 8096 1482 * @Default: 1024 1483 * 1484 * This ini sets the tx comp ring size for IPA 1485 * 1486 * Related: N/A 1487 * 1488 * Supported Feature: IPA 1489 * 1490 * Usage: Internal 1491 * 1492 * </ini> 1493 */ 1494 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1495 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1496 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1497 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1498 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1499 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1500 1501 #ifdef IPA_WDI3_TX_TWO_PIPES 1502 /* 1503 * <ini> 1504 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1505 * @Min: 1024 1506 * @Max: 8096 1507 * @Default: 1024 1508 * 1509 * This ini sets the alt tcl ring size for IPA 1510 * 1511 * Related: N/A 1512 * 1513 * Supported Feature: IPA 1514 * 1515 * Usage: Internal 1516 * 1517 * </ini> 1518 */ 1519 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1520 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1521 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1522 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1523 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1524 CFG_VALUE_OR_DEFAULT, \ 1525 "DP IPA TX Alternative Ring Size") 1526 1527 /* 1528 * <ini> 1529 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1530 * @Min: 1024 1531 * @Max: 8096 1532 * @Default: 1024 1533 * 1534 * This ini sets the tx alt comp ring size for IPA 1535 * 1536 * Related: N/A 1537 * 1538 * Supported Feature: IPA 1539 * 1540 * Usage: Internal 1541 * 1542 * </ini> 1543 */ 1544 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1545 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1546 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1547 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1548 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1549 CFG_VALUE_OR_DEFAULT, \ 1550 "DP IPA TX Alternative Completion Ring Size") 1551 1552 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1553 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1554 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1555 1556 #else 1557 #define CFG_DP_IPA_TX_ALT_RING_CFG 1558 #endif 1559 1560 #define CFG_DP_IPA_TX_RING_CFG \ 1561 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1562 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1563 #else 1564 #define CFG_DP_IPA_TX_RING_CFG 1565 #define CFG_DP_IPA_TX_ALT_RING_CFG 1566 #endif 1567 1568 #ifdef WLAN_SUPPORT_PPEDS 1569 #define CFG_DP_PPE_ENABLE \ 1570 CFG_INI_BOOL("ppe_enable", false, \ 1571 "DP ppe enable flag") 1572 1573 #define CFG_DP_REO2PPE_RING \ 1574 CFG_INI_UINT("dp_reo2ppe_ring", \ 1575 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1576 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1577 WLAN_CFG_REO2PPE_RING_SIZE, \ 1578 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1579 1580 #define CFG_DP_PPE2TCL_RING \ 1581 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1582 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1583 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1584 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1585 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1586 1587 #define CFG_DP_PPE_RELEASE_RING \ 1588 CFG_INI_UINT("dp_ppe_release_ring", \ 1589 WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN, \ 1590 WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX, \ 1591 WLAN_CFG_PPE_RELEASE_RING_SIZE, \ 1592 CFG_VALUE_OR_DEFAULT, "DP PPE Release Ring") 1593 1594 #define CFG_DP_PPE_CONFIG \ 1595 CFG(CFG_DP_PPE_ENABLE) \ 1596 CFG(CFG_DP_REO2PPE_RING) \ 1597 CFG(CFG_DP_PPE2TCL_RING) \ 1598 CFG(CFG_DP_PPE_RELEASE_RING) 1599 #else 1600 #define CFG_DP_PPE_CONFIG 1601 #endif 1602 1603 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1604 /* 1605 * <ini> 1606 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1607 * @Min: 0x0 1608 * @Max: 0xFF 1609 * @Default: 0xF 1610 * 1611 * This ini sets Rx ring map for CHIP 0 1612 * 1613 * Usage: Internal 1614 * 1615 * </ini> 1616 */ 1617 #define CFG_DP_MLO_CHIP0_RX_RING_MAP \ 1618 CFG_INI_UINT("dp_chip0_rx_ring_map", \ 1619 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1620 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1621 WLAN_CFG_MLO_RX_RING_MAP, \ 1622 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip0") 1623 1624 /* 1625 * <ini> 1626 * dp_chip1_rx_ring_map - Set Rx ring map for CHIP 1 1627 * @Min: 0x0 1628 * @Max: 0xFF 1629 * @Default: 0xF 1630 * 1631 * This ini sets Rx ring map for CHIP 1 1632 * 1633 * Usage: Internal 1634 * 1635 * </ini> 1636 */ 1637 #define CFG_DP_MLO_CHIP1_RX_RING_MAP \ 1638 CFG_INI_UINT("dp_chip1_rx_ring_map", \ 1639 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1640 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1641 WLAN_CFG_MLO_RX_RING_MAP, \ 1642 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip1") 1643 1644 /* 1645 * <ini> 1646 * dp_chip2_rx_ring_map - Set Rx ring map for CHIP 2 1647 * @Min: 0x0 1648 * @Max: 0xFF 1649 * @Default: 0xF 1650 * 1651 * This ini sets Rx ring map for CHIP 2 1652 * 1653 * Usage: Internal 1654 * 1655 * </ini> 1656 */ 1657 #define CFG_DP_MLO_CHIP2_RX_RING_MAP \ 1658 CFG_INI_UINT("dp_chip2_rx_ring_map", \ 1659 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1660 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1661 WLAN_CFG_MLO_RX_RING_MAP, \ 1662 CFG_VALUE_OR_DEFAULT, "DP Rx ring map chip2") 1663 1664 #define CFG_DP_MLO_CONFIG \ 1665 CFG(CFG_DP_MLO_CHIP0_RX_RING_MAP) \ 1666 CFG(CFG_DP_MLO_CHIP1_RX_RING_MAP) \ 1667 CFG(CFG_DP_MLO_CHIP2_RX_RING_MAP) 1668 #else 1669 #define CFG_DP_MLO_CONFIG 1670 #endif 1671 1672 /* 1673 * <ini> 1674 * dp_mpdu_retry_threshold_1 - threshold to increment mpdu success with retries 1675 * @Min: 0 1676 * @Max: 255 1677 * @Default: 0 1678 * 1679 * This ini entry is used to set first threshold to increment the value of 1680 * mpdu_success_with_retries 1681 * 1682 * Usage: Internal 1683 * 1684 * </ini> 1685 */ 1686 #define CFG_DP_MPDU_RETRY_THRESHOLD_1 \ 1687 CFG_INI_UINT("dp_mpdu_retry_threshold_1", \ 1688 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1689 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1690 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1691 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 1") 1692 1693 /* 1694 * <ini> 1695 * dp_mpdu_retry_threshold_2 - threshold to increment mpdu success with retries 1696 * @Min: 0 1697 * @Max: 255 1698 * @Default: 0 1699 * 1700 * This ini entry is used to set second threshold to increment the value of 1701 * mpdu_success_with_retries 1702 * 1703 * Usage: Internal 1704 * 1705 * </ini> 1706 */ 1707 #define CFG_DP_MPDU_RETRY_THRESHOLD_2 \ 1708 CFG_INI_UINT("dp_mpdu_retry_threshold_2", \ 1709 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1710 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1711 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1712 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 2") 1713 1714 #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES 1715 /* Macro enabling support marking of notify frames by host */ 1716 #define DP_MARK_NOTIFY_FRAME_SUPPORT 1 1717 #else 1718 #define DP_MARK_NOTIFY_FRAME_SUPPORT 0 1719 #endif /* QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES */ 1720 1721 /* 1722 * <ini> 1723 * Host DP AST entries database - Enable/Disable 1724 * 1725 * @Default: 0 1726 * 1727 * This ini enables/disables AST entries database on host 1728 * 1729 * Usage: Internal 1730 * 1731 * </ini> 1732 */ 1733 #define CFG_DP_HOST_AST_DB_ENABLE \ 1734 CFG_INI_BOOL("host_ast_db_enable", false, \ 1735 "Host AST entries database Enable/Disable") 1736 1737 #define CFG_DP \ 1738 CFG(CFG_DP_HTT_PACKET_TYPE) \ 1739 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 1740 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 1741 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 1742 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 1743 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 1744 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 1745 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 1746 CFG(CFG_DP_MAX_CLIENTS) \ 1747 CFG(CFG_DP_MAX_PEER_ID) \ 1748 CFG(CFG_DP_REO_DEST_RINGS) \ 1749 CFG(CFG_DP_TX_COMP_RINGS) \ 1750 CFG(CFG_DP_TCL_DATA_RINGS) \ 1751 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 1752 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 1753 CFG(CFG_DP_TX_DESC) \ 1754 CFG(CFG_DP_TX_EXT_DESC) \ 1755 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 1756 CFG(CFG_DP_PDEV_RX_RING) \ 1757 CFG(CFG_DP_PDEV_TX_RING) \ 1758 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 1759 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 1760 CFG(CFG_DP_TX_RING_SIZE) \ 1761 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 1762 CFG(CFG_DP_PDEV_LMAC_RING) \ 1763 CFG(CFG_DP_BASE_HW_MAC_ID) \ 1764 CFG(CFG_DP_RX_HASH) \ 1765 CFG(CFG_DP_TSO) \ 1766 CFG(CFG_DP_LRO) \ 1767 CFG(CFG_DP_SG) \ 1768 CFG(CFG_DP_GRO) \ 1769 CFG(CFG_DP_TC_INGRESS_PRIO) \ 1770 CFG(CFG_DP_OL_TX_CSUM) \ 1771 CFG(CFG_DP_OL_RX_CSUM) \ 1772 CFG(CFG_DP_RAWMODE) \ 1773 CFG(CFG_DP_PEER_FLOW_CTRL) \ 1774 CFG(CFG_DP_NAPI) \ 1775 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 1776 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 1777 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 1778 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 1779 CFG(CFG_DP_WBM_RELEASE_RING) \ 1780 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 1781 CFG(CFG_DP_TCL_STATUS_RING) \ 1782 CFG(CFG_DP_REO_REINJECT_RING) \ 1783 CFG(CFG_DP_RX_RELEASE_RING) \ 1784 CFG(CFG_DP_REO_EXCEPTION_RING) \ 1785 CFG(CFG_DP_RX_DESTINATION_RING) \ 1786 CFG(CFG_DP_REO_CMD_RING) \ 1787 CFG(CFG_DP_REO_STATUS_RING) \ 1788 CFG(CFG_DP_RXDMA_BUF_RING) \ 1789 CFG(CFG_DP_RXDMA_REFILL_RING) \ 1790 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 1791 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 1792 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 1793 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 1794 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 1795 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 1796 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 1797 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 1798 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 1799 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 1800 CFG(CFG_DP_PER_PKT_LOGGING) \ 1801 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 1802 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 1803 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 1804 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 1805 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 1806 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 1807 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 1808 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 1809 CFG(CFG_DP_RX_SW_DESC_NUM) \ 1810 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 1811 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 1812 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 1813 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 1814 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 1815 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 1816 CFG(CFG_DP_RX_FISA_ENABLE) \ 1817 CFG(CFG_DP_RX_FISA_LRU_DEL_ENABLE) \ 1818 CFG(CFG_DP_FULL_MON_MODE) \ 1819 CFG(CFG_DP_REO_RINGS_MAP) \ 1820 CFG(CFG_DP_PEER_EXT_STATS) \ 1821 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 1822 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 1823 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 1824 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 1825 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 1826 CFG(CFG_DP_POLL_MODE_ENABLE) \ 1827 CFG(CFG_DP_SWLM_ENABLE) \ 1828 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 1829 CFG(CFG_DP_RX_FST_IN_CMEM) \ 1830 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 1831 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 1832 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 1833 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 1834 CFG(CFG_DP_HW_CC_ENABLE) \ 1835 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 1836 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 1837 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 1838 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_1) \ 1839 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_2) \ 1840 CFG_DP_IPA_TX_RING_CFG \ 1841 CFG_DP_PPE_CONFIG \ 1842 CFG_DP_IPA_TX_ALT_RING_CFG \ 1843 CFG_DP_MLO_CONFIG \ 1844 CFG_DP_INI_SECTION_PARAMS \ 1845 CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1846 CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) \ 1847 CFG(CFG_DP_NAPI_SCALE_FACTOR) \ 1848 CFG(CFG_DP_HOST_AST_DB_ENABLE) 1849 #endif /* _CFG_DP_H_ */ 1850